Chip structure
View Patent ↗A chip structure includes a semiconductor substrate, an interconnecting metallization structure, a passivation layer, a circuit layer and a bump. The interconnecting metallization structure is over the semiconductor substrate. The passivation layer is over the interconnecting metallization structure. The circuit layer is over the passivation layer. The bump is on the circuit layer, and the bump is unsuited for being processed using a reflow process.
1. A circuit component comprising:
a semiconductor chip comprising a semiconductor substrate, a transistor in or on said semiconductor substrate, a first metal interconnect over said semiconductor substrate, a second metal interconnect over said semiconductor substrate, a third metal interconnect over said semiconductor substrate, wherein said first metal interconnect comprises a damascene copper layer, a first insulating layer over said semiconductor substrate, wherein a first opening in said first insulating layer is over a first contact point of said first metal interconnect, and said first contact point is at a bottom of said first opening, wherein a second opening in said first insulating layer is over a second contact point of said second metal interconnect, and said second contact point is at a bottom of said second opening, and wherein a third opening in said first insulating layer is over a third contact point of said third metal interconnect, and said third contact point is at a bottom of said third opening, a fourth metal interconnect on said first and second contact points and over said first insulating layer, wherein said first contact point is connected to said second contact point through said fourth metal interconnect, a second insulating layer over said fourth metal interconnect and said first insulating layer, wherein said second insulating layer contacts a top surface and a sidewall of said fourth metal interconnect, and a metal bump connected to said third contact point through said third opening; and
a glass substrate over said semiconductor chip and said metal bump.
2. The circuit component of claim 1 , wherein said metal bump comprises a copper layer.
3. The circuit component of claim 1 , wherein said first insulating layer comprises an oxide layer having a thickness between 0.1 and 0.8 micrometers.
4. The circuit component of claim 1 , wherein a material of said fourth metal interconnect is different from that of said first metal interconnect.
5. The circuit component of claim 1 , wherein said first insulating layer comprises an oxide layer.
6. The circuit component of claim 1 , wherein said first insulating layer comprises a nitride layer.
7. The circuit component of claim 1 , wherein said first insulating layer comprises an oxide layer and a nitride layer over said oxide layer.
8. The circuit component of claim 1 , wherein said second insulating layer comprises a polymer layer.
9. The circuit component of claim 1 , wherein said second insulating layer has a top surface lower than that of said metal bump.
10. The circuit component of claim 1 , wherein said fourth metal interconnect has a top surface lower than that of said metal bump.
11. The circuit component of claim 1 , further comprising a circuit layer under said glass substrate and over said metal bump, wherein said metal bump is connected to said circuit layer.
12. The circuit component of claim 11 , further comprising multiple metal particles between said metal bump and said circuit layer.
13. The circuit component of claim 1 , further comprising an anisotropic conductive film (ACF) between said semiconductor chip and said glass substrate.
14. The circuit component of claim 1 , wherein said metal bump comprises a tin-and-silver-containing alloy.
15. The circuit component of claim 1 , wherein said metal bump comprises a gold layer having a thickness between 7 and 100 micrometers.
16. The circuit component of claim 1 , wherein said metal bump comprises a copper layer having a thickness between 7 and 100 micrometers.
17. The circuit component of claim 1 , wherein said metal bump comprises a tin-containing alloy having a thickness between 25 and 300 micrometers.
18. The circuit component of claim 1 , wherein said metal bump comprises a titanium-containing layer and a metal layer on said titanium-containing layer.
19. The circuit component of claim 1 , wherein said fourth metal interconnect comprises a gold layer having a thickness between 2 and 30 micrometers.
20. The circuit component of claim 1 , wherein said fourth metal interconnect comprises a copper layer having a thickness between 2 and 30 micrometers.
21. The circuit component of claim 1 , wherein said fourth metal interconnect comprises a titanium-containing layer and a metal layer on said titanium-containing layer.