IP Library Granted Patent US 8,902,653
Granted Patent B2
US 8,902,653 · App. 13/208,802 · Granted Dec 2, 2014

Memory devices and configuration methods for a memory device

Inventors: William H. Radke (Los Gatos, CA); Tommaso Vali (Latina, IT); Michele Incarnati (Gioia dei Marsi, IT)
Assignee: Micron Technology, Inc.
G11C16/10G11C11/5628G06F11/1048G11C16/0483
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Quick Facts
Patent No.
US 8,902,653
App. No.
13/208,802
Granted
Dec 2, 2014
Kind
B2
Abstract

Memory devices and methods of operating memory devices are disclosed. In one such method, different blocks of memory cells have different configurations of user data space and overhead data space. In at least one method, overhead data is distributed within more than one block of memory cells. In another method, blocks are reconfigurable responsive to particular operating modes and/or desired levels of reliability of user data stored in a memory device.

Claims (31)

1. A method of operating a memory device having an array of memory cells logically arranged in rows and in columns, the method comprising:

configuring a particular number of memory cells of a first row as user data memory cells;

configuring a first group of memory cells to store overhead data specific to user data to be stored in the particular number of user data memory cells; and

configuring a second group of memory cells to store overhead data specific to the user data to be stored in the particular number of user data memory cells, where the first group of memory cells comprise memory cells of the first row and the second group of memory cells comprise memory cells of a second row of memory cells.

2. The method of claim 1 , wherein configuring the particular number of memory cells of the first row further comprises allocating a page of user data memory cells.

3. The method of claim 1 , wherein configuring the particular number of memory cells further comprises allocating the particular number of memory cells in response to a desired page size.

4. The method of claim 1 , wherein configuring the particular number of memory cells further comprises allocating the particular number of memory cells in response to a particular operating mode of the memory device.

5. The method of claim 4 , wherein allocating the particular number of memory cells in response to the particular operating mode further comprises allocating a different particular number of memory cells in response to changing an operating mode of the memory device.

6. The method of claim 1 , wherein configuring the particular number of memory cells as user data memory cells further comprises allocating a particular number of memory cells comprising memory cells of the first and second rows of memory cells.

7. The method of claim 1 , wherein configuring the first group of memory cells to store overhead data specific to the user data comprises configuring the first group of memory cells to store error correction code (ECC) data specific to the user data, and wherein configuring the second group of memory cells to store overhead data specific to the user data comprises configuring the second group of memory cells to store ECC data specific to the user data.

8. The method of claim 1 , wherein configuring the second group of memory cells to store overhead data specific to the user data is in response to determining that the first group of memory cells is insufficient to store all of the overhead data specific to the user data.

9. The method of claim 1 , further comprising programming the user data memory cells as multi-level cells with the user data, and programming the first group of memory cells and the second group of memory cells as single-level memory cells with the overhead data.

10. A method of operating a memory device having an array of memory cells logically arranged in rows and in columns, the method comprising:

configuring a particular number of memory cells of a first row as user data memory cells;

configuring a first group of memory cells to store a first portion of overhead data specific to and that is generated from user data to be stored in the particular number of user data memory cells; and

configuring a second group of memory cells to store a second portion of the overhead data specific to and that is generated from the user data to be stored in the particular number of user data memory cells, where the first group of memory cells comprise memory cells of the first row and the second group of memory cells comprise memory cells of a second row of memory cells.

11. The method of claim 10 , wherein the first and second portions of the overhead data are first and second portions of error correction code (ECC) data.

12. The method of claim 11 , wherein the first and second portions of ECC data are generated from the user data in response to applying an ECC scheme to the user data.

13. The method of claim 12 , wherein the ECC scheme is selected in response to a type of data to be stored in the user data memory cells.

14. The method of claim 12 , wherein the ECC scheme is selected in response to a desired level of reliability of user data to be read from the user data memory cells.

15. The method of claim 10 , wherein a number of memory cells in the first group of memory cells and a number of memory cells in the second group of memory cells are dependent upon the particular number of memory cells of the first row configured as user data memory cells.

16. The method of claim 10 , wherein configuring the second group of memory cells to store the second portion of overhead data is in response to determining that the first group of memory cells is insufficient to store the second portion of overhead data.

17. A method of operating a memory device having an array of memory cells logically arranged in rows and in columns, the method comprising:

configuring a particular number of memory cells of a first row as user data memory cells;

assigning a scheme having a desired resolution to the user data memory cells;

configuring a first group of memory cells to store overhead data specific to user data to be stored in the particular number of user data memory cells; and

configuring a second group of memory cells to store overhead data specific to the user data to be stored in the particular number of user data memory cells, where the first group of memory cells comprise memory cells of the first row and the second group of memory cells comprise memory cells of a second row of memory cells;

wherein the overhead data specific to the user data is generated responsive to applying the assigned scheme to the user data to be stored in the user data memory cells.

18. The method of claim 17 , wherein the assigned scheme comprises an error correction code (ECC) scheme and the overhead data specific to the user data comprises ECC data specific to the user data.

19. The method of claim 17 , wherein configuring the first group of memory cells and configuring the second group of memory cells to store the overhead data specific to the user data comprises allocating a number of memory cells to store the overhead data specific to the user data based on the desired resolution.

20. The method of claim 17 , further comprising programming the user data memory cells as multi-level cells with the user data, and programming the first and second groups of memory cells as single-level memory cells with the generated overhead data.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 12, 2011
From: RADKE, WILLIAM H.; VALI, TOMMASO; INCARNATI, MICHELE
To: MICRON TECHNOLOGY, INC.
Reel/Frame 026744/0194 →
Continuity (1)
Related Publication 20130039129A1 · Feb 14, 2013