Methods for fabricating FinFET integrated circuits in bulk semiconductor substrates

1. A method for fabricating a FinFET integrated circuit comprising:

providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines;

etching the semiconductor substrate to form a plurality of fins, each of the plurality of fins extending across the width of the chips substantially to the scribe lines;

depositing an oxide to fill between the fins;

etching the oxide to recess the oxide;

oxidizing the plurality of fins;

depositing and patterning an isolation hard mask overlying the plurality of fins;

etching the semiconductor substrate using the isolation hard mask as an etch mask to form trenches in the semiconductor substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins; and

filling the trenches with an insulating material to isolate between adjacent ones of the plurality of active areas,

wherein oxidizing the plurality of fins is performed after etching the oxide and before depositing and patterning an isolation hard mask.

2. The method of claim 1 wherein etching the semiconductor substrate comprises:

depositing and patterning a layer of hard mask material to form a plurality of hard mask lines having substantially uniform pitch and spacing;

anisotropically etching the semiconductor substrate using plurality of hard mask lines as an etch mask to form the plurality of fins.

3. The method of claim 2 wherein depositing an oxide comprises:

depositing a layer of oxide overlying the plurality of hard mask lines and the plurality of fins and filling between the plurality of fins;

planarizing the layer of oxide using the plurality of hard mask lines as a planarization stop; and

further planarizing to remove the plurality of hard mask lines and to stop substantially at the plurality of fins.

4. The method of claim 1 wherein etching the semiconductor substrate comprises etching the semiconductor substrate to form fins having a height of 40-100 nm and a width of 10-20 nm.

5. The method of claim 1 wherein etching the oxide comprises etching the oxide to expose 10-30 nm of the plurality of fins.

6. The method of claim 1 wherein filling the trenches comprises:

depositing a trench liner;

depositing a gap fill oxide overlying the trench liner;

planarizing the gap fill oxide and stopping the planarization on the isolation hard mask;

etching the gap fill oxide to recess the gap fill oxide to substantially the height of the oxide between the plurality of fins; and

removing the isolation hard mask.

7. The method of claim 1 further comprising:

forming a gate insulator overlying the at least a portion of at least one of the plurality of fins; and

forming a gate electrode overlying the gate insulator.

8. The method of claim 7 further comprising impurity doping source and drain regions in the at least a portion of at least one of the plurality of fins in self alignment with the gate electrode.

9. A method for fabricating a FinFET integrated circuit comprising:

providing a semiconductor substrate divided into a plurality of chip areas;

etching the semiconductor substrate to form a plurality of fins extending across each chip area;

forming isolation between adjacent ones of the plurality of fins;

oxidizing the plurality of fins;

etching through the plurality of fins and into the semiconductor substrate to form trenches in the semiconductor substrate and to divide the plurality of fins into fins of predetermined length; and

filling the trenches with insulating material, wherein filling the trenches comprises:

depositing a trench liner;

depositing a gap fill oxide overlying the trench liner;

planarizing the gap fill oxide; and

etching the gap fill oxide to recess the gap fill oxide to substantially the height of the isolation between the plurality of fins.

10. The method of claim 9 wherein etching the semiconductor substrate comprises:

forming a silicon nitride hard mask overlying the semiconductor substrate; and

anisotropically etching the semiconductor substrate using the hard mask as an etch mask.

11. The method of claim 10 wherein forming isolation comprises:

depositing a layer of oxide overlying the plurality of fins;

planarizing the layer of oxide by chemical mechanical planarization and stopping the planarization on the hard mask; and

etching the planarized layer of oxide to recess the top of the oxide below the top of the plurality of fins.

12. The method of claim 10 wherein forming isolation comprises:

depositing a layer of oxide overlying the plurality of fins;

planarizing the layer of oxide and removing the hard mask by chemical mechanical planarization and stopping the planarization at the top of the plurality of fins; and

etching the planarized layer of oxide to recess the top of the oxide below the top of the plurality of fins.

13. The method of claim 9 further comprising forming gate structures overlying the fins of predetermined length.

14. A method for fabricating a FinFET integrated circuit comprising:

providing a semiconductor substrate divided into a plurality of chips, each chip bounded by scribe lines;

etching the semiconductor substrate to form a plurality of fins, each of the plurality of fins extending across the width of the chips substantially to the scribe lines;

depositing an oxide to fill between the fins;

etching the oxide to recess the oxide;

depositing and patterning an isolation hard mask overlying the plurality of fins;

etching the semiconductor substrate using the isolation hard mask as an etch mask to form trenches in the semiconductor substrate defining a plurality of active areas, each of the plurality of active areas including at least a portion of at least one of the fins; and

filling the trenches with an insulating material to isolate between adjacent ones of the plurality of active areas,

wherein filling the trenches comprises:

depositing a trench liner;

depositing a gap fill oxide overlying the trench liner;

planarizing the gap fill oxide and stopping the planarization on the isolation hard mask;

etching the gap fill oxide to recess the gap fill oxide to substantially the height of the oxide between the plurality of fins; and

removing the isolation hard mask.

15. The method of claim 14 wherein etching the semiconductor substrate comprises:

depositing and patterning a layer of hard mask material to form a plurality of hard mask lines having substantially uniform pitch and spacing;

anisotropically etching the semiconductor substrate using plurality of hard mask lines as an etch mask to form the plurality of fins.

16. The method of claim 15 wherein depositing an oxide comprises:

depositing a layer of oxide overlying the plurality of hard mask lines and the plurality of fins and filling between the plurality of fins;

planarizing the layer of oxide using the plurality of hard mask lines as a planarization stop; and

further planarizing to remove the plurality of hard mask lines and to stop substantially at the plurality of fins.

17. The method of claim 14 wherein etching the semiconductor substrate comprises etching the semiconductor substrate to form fins having a height of 40-100 nm and a width of 10-20 nm.

18. The method of claim 14 wherein etching the oxide comprises etching the oxide to expose 10-30 nm of the plurality of fins.

19. The method of claim 14 further comprising:

forming a gate insulator overlying the at least a portion of at least one of the plurality of fins; and

forming a gate electrode overlying the gate insulator.

20. The method of claim 19 further comprising impurity doping source and drain regions in the at least a portion of at least one of the plurality of fins in self alignment with the gate electrode.