Edge termination region of a semiconductor device
View Patent ↗An isolation region ( 14 ) is formed between an edge termination region ( 2 ) having deep trenches ( 20,34 ) and the central region ( 4 ). The isolation region includes gate fingers ( 18 ) extending from the edge gate trench regions ( 28 ) to the gate trenches ( 6 ) in the central region ( 4 ) to electrically connect the edge gate trench regions to the gate trenches ( 6 ) in the central region. The isolation region also includes isolation fingers ( 22,24 ) extending from the edge termination region ( 2 ) towards the central region ( 4 ) and gate between the gate fingers ( 18 ) for reducing the breakdown voltage with a RESURF effect.
1. A semiconductor device having an edge termination region, the device comprising:
a central active region forming at least one field effect transistor with a semiconductor body having a source, drain and gate,
an edge termination region including at least one deep trench region and a plurality of edge gate trench regions, the edge gate trench regions comprising an insulated gate in a trench; and
an isolation region between the edge termination region and the central active region, the isolation region comprising gate fingers extending from the edge gate trench regions to gate trenches in the central region to electrically connect the edge gate trench regions to the gate trenches in the central region, and the isolation region further comprising conductive isolation fingers extending from the edge termination region towards the central region and gate between the gate fingers.
2. A semiconductor device according to claim 1 , wherein the source is of first conductivity type, connected to a source metal through a plurality of source contacts, the semiconductor device further comprising a region of second conductivity type extending into the semiconductor body from the source contacts arranged to reduce the breakdown voltage in the central region.
3. A semiconductor device according to claim 2 wherein the source metal is further connected to trench contacts on the isolation fingers to connect the isolation fingers to the source.
4. A semiconductor device according to claim 1 , further comprising a gate metal over the edge gate trench regions connected to the edge gate trench regions through a gate contact on the edge gate trench regions to provide a gate connection to the semiconductor device.
5. A semiconductor device according to claim 1 wherein the central region includes a plurality of source contacts at a source pitch, and the pitch of the plurality of edge gate trench regions is greater than the source pitch.
6. A semiconductor device according claim 1 , further comprising an n-well in the edge termination region.
7. A semiconductor device according to claim 1 further comprising a gate metal over the edge termination region directly in contact with gate contacts in the edge gate trench regions to provide a gate connection to the semiconductor device.
8. A semiconductor device according to claim 1 , wherein the fingers include:
a first set of isolation fingers being extensions of the deep trench regions, and
a second set of isolation fingers being separated from the deep trench isolation regions by the edge gate trench regions and alternating with the first set of isolation fingers.
9. A semiconductor device according to claim 1 , wherein the isolation fingers are each extensions of the deep trench regions and
the isolation fingers alternate with the edge gate trench regions.
10. A semiconductor device according to claim 1 , wherein at least some of the isolation fingers have an outer region being an extension of the deep trench region, and an inner region separated from the outer region by a finger semiconductor region,
further comprising a source contact in each of the outer region, the finger semiconductor region and the inner region of at least some of the isolation fingers, the source contacts being connected to source metal.
11. A method of manufacturing a semiconductor device, comprising:
(a) forming a central active region with at least one field effect transistor with a semiconductor body of a first conductivity type, the field effect transistor having a source, drain and gate,
(b) forming an edge termination region including at least one deep trench isolation region and a plurality of edge gate trench regions, the edge gate trench regions comprising an insulated gate in a trench;
(c) forming an isolation region between the edge termination region and the central active region, the isolation region comprising gate fingers extending from the edge gate trench regions to gate in the central region and the isolation region further comprising conductive isolation fingers extending from the edge termination region towards the central region and gate between the gate fingers;
where steps (a), (b), and (c) can take place in any order and/or concurrently, the method further comprising:
(d) depositing an insulating layer;
(e) forming contact openings in the insulating layer; and
(f) implanting regions of a second conductivity type opposite to the first conductivity type through the contact openings arranged to reduce the breakdown voltage of the device.
12. A method according to claim 11 including implanting over the complete semiconductor device a region of first conductivity type of higher doping concentration than the semiconductor body to form the source in the central region.
13. A method according to claim 11 further comprising implanting a counter doping of second conductivity type in the edge termination region to reduce the doping of first conductivity type at the surface of the semiconductor in the edge termination region.