Semiconductor package containing silicon-on-insulator die mounted in bump-on-leadframe manner to provide low thermal resistance
View Patent ↗Thermal transfer from a silicon-on-insulator (SOI) die is improved by mounting the die in a bump-on-leadframe manner in a semiconductor package, with solder or other metal bumps connecting the active layer of the SOI die to metal leads used to mount the package on a printed circuit board or other support structure.
1. A semiconductor package comprising:
a lead;
a silicon-on-insulator (SOI) die, the SOI die comprising an insulating layer sandwiched between a handle layer and an active layer, the handle layer having a first surface in contact with the insulating layer and a second surface opposite to the first surface, the SOI die being oriented in the package with the active layer facing the lead; and
a metal bump connecting a contact pad at a surface of the active layer with the lead, the contact pad being formed in a thermal island in the active layer, the thermal island being defined by at least one dielectric filled trench, the trench extending between the surface of the active layer and the insulating layer and being laterally enclosed within the active layer, the SOI die, the metal bump and at least a portion of the lead being encased in a molding compound, the molding compound completely covering the second surface of the handle layer.
2. The semiconductor package of claim 1 wherein the thermal island is surrounded by a double trench.
3. The semiconductor package of claim 1 wherein the thermal island contains at least one semiconductor device.
4. The semiconductor package of claim 1 wherein the lead protrudes from an outside surface of the molding compound.
5. The semiconductor package of claim 4 further comprising a heat slug and a second metal bump, the second metal bump connecting a second contact pad at the surface of the active layer with the heat slug, the heat slug having an exposed surface coplanar with and surrounded by a bottom surface of the molding compound.
6. The semiconductor package of claim 5 wherein a horizontal cross-sectional area of the heat slug is at least five times greater than an area of the lead taken at a cross-section perpendicular to a wall of the lead.
7. The semiconductor package of claim 1 wherein the semiconductor package comprises a DFN-type package, the lead having at least one surface coplanar with an outside surface of the molding compound.
8. The semiconductor package of claim 7 further comprising a heat slug and a second metal bump, the second metal bump connecting a second contact pad at the surface of the active layer with the heat slug, the heat slug having an exposed surface coplanar with and surrounded by a bottom surface of the molding compound.
9. The semiconductor package of claim 8 wherein a horizontal cross-sectional area of the heat slug is at least five times greater than an area of the lead taken at a cross-section perpendicular to a wall of the lead.
10. The semiconductor package of claim 8 wherein the contact pad is formed in a thermal island in the active layer, the thermal island being surrounded by at least one trench extending between the surface of the active layer and the insulating layer, the trench being filed with a dielectric material, and wherein the second contact pad is formed in a second thermal island in the active layer, the second thermal island being surrounded by at least one second trench extending between the surface of the active layer and the oxide layer, the second trench being filed with the dielectric material.
11. The semiconductor package of claim 10 wherein the thermal island contains at least one semiconductor device.