IP Library Granted Patent US 8,493,097
Granted Patent B2
US 8,493,097 · App. 13/211,055 · Granted Jul 23, 2013

Current-sensing circuit

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Quick Facts
Patent No.
US 8,493,097
App. No.
13/211,055
Granted
Jul 23, 2013
Kind
B2
Abstract

In one embodiment, a circuit is provided. The circuit includes a low-ohmic circuit and a a power supply node configured and arranged for providing a supply voltage across the low-ohmic circuit to a load from which current can be drawn. The circuit also includes a current reference circuit, configured and arranged for setting a current reference level that is based on a portion of the current from the power supply node, and a current-sensing circuit. The current-sensing circuit senses and is responsive to current passing through the low-ohmic circuit. The current-sensing circuit operates in a normal mode, in which the current-sensing circuit senses an amount of current passing through the low ohmic circuit that is less than the current threshold level, and in an over-current mode, in which the current-sensing circuit senses an amount of current passing through the low ohmic circuit that is greater than the current threshold level.

Claims (48)

1. A circuit comprising:

a low-ohmic circuit;

a power supply node configured and arranged for providing a supply voltage across the low-ohmic circuit to a load (“other blocks”) from which current can be drawn;

a current reference circuit configured and arranged for setting a current threshold level based on and drawing a portion of the current from the power supply node; and

a current-sensing circuit, responsive to and sensing current through the low-ohmic circuit, configured and arranged for operating in a normal mode, in which the current-sensing circuit senses an amount of current passing through the low-ohmic circuit that is less than the current threshold level, and in an over-current mode, in which the current-sensing circuit senses an amount of current passing through the low-ohmic circuit that is greater than the current threshold level.

2. The circuit of claim 1 , wherein the low-ohmic circuit includes an FET-based switch and does not include a resistor.

3. The circuit of claim 1 , wherein the current reference circuit has at least one cell with a mirror circuit.

4. The circuit of claim 1 , wherein:

the current reference circuit has an output node configured and arranged for providing the current reference level and has at least two stages;

each of said at least two stages including a respective current mirror;

a first one of the at least two stages having a resistor configured and arranged to compensate the temperature coefficient; and

a second one of the at least two stages having a transistor-based structure configured and arranged to lower the process variation of an output current of the output node, a gate voltage of the transistor-based structure controlled by an output current of the first one of the two stages.

5. The circuit of claim 4 , wherein each of the at least two stages includes an additional current mirror coupled to the first mentioned current mirror in a cascade arrangement.

6. The circuit of claim 4 , wherein the current reference circuit further includes an additional stage having a current mirror and a transistor-based structure configured and arranged to lower process variation of the output current of the output node, a gate voltage of the transistor-based structure of the additional stage being controlled by an output current of the second of the at least two stages.

7. The circuit of claim 1 wherein:

the low-ohmic circuit is a power switch;

the current sensing circuit is configured and arranged to generate a signal in response to operating in the over-current state of operation; and

the power switch is configured and arranged to break a current path to the load in response to the signal.

8. A circuit comprising:

a transistor-based switch located on a current path from a supply voltage, through a load coupled to the circuit, to a ground voltage, the transistor-based switch having a first source/drain and a second source/drain, the first source/drain having a first voltage greater than a second voltage of the second source/drain;

a reference transistor having a first source/drain coupled to the first voltage and a second source/drain having a third voltage; and

a current-sensing circuit, responsive to and sensing current through the transistor-based switch via a pair of current paths, including a first current path from the second voltage to the ground voltage and a second current path from the third voltage to the ground voltage, the current-sensing circuit is configured and arranged for operating in a normal mode, in which the current-sensing circuit senses an amount of current passing through the transistor based switch that is less than a current threshold level, and in an over-current mode, in which an amount of current passing through the transistor based switch is greater than the current threshold level, the current threshold level being equal to a current passing through the second current path scaled by a ratio of a transconductance of the reference transistor to a transconductance of the transistor based switch.

9. The circuit of claim 8 , further including a control circuit and an output signal configured and arranged to indicate which of the two modes is in operation, where the control circuit is configured and arranged to respond to the output signal by generating a signal that causes the transistor-based switch to break a current path to the load.

10. The circuit of claim 8 , wherein a current-reactive circuit includes an FET-based circuit configured and arranged to cause switching between the normal and over-current modes by transitioning the FET-based circuit between linear and saturation operation regions.

11. The circuit of claim 8 , wherein the current-sensing circuit includes a current mirror having a first transistor on the first current path and a second transistor on the second current path.

12. The circuit of claim 11 , wherein:

the first and second transistors of the current mirror are PMOS transistors; and

the current-sensing circuit includes a biasing circuit configured and arranged to bias a current on each of the first and second current paths of the current-sensing circuit according to a reference current generated by a current reference circuit, such that a gate to source voltage of the first transistor of the current mirror is inversely proportional to the current passing through the transistor based switch.

13. The circuit of claim 12 , wherein the current-sensing circuit is configured and arranged to bias the current on each of the first and second current paths of the current-sensing circuit to be equal to the current threshold level scaled by a ratio of a transconductance of the transistor based switch to a transconductance of the reference transistor.

14. The circuit of claim 12 , wherein the biasing circuit includes:

a second current mirror located on each of the first and second current paths between the first mentioned current mirror and the ground voltage, the second current mirror configured and arranged to bias current on the first current path according to the current reference level and bias current on the second current path according to the current reference level.

15. The circuit of claim 14 , wherein

the current-sensing circuit includes:

an output node located between the first and second current mirrors on the first current path of the sensing circuit;

a third current mirror located between the first mentioned current mirror and the output node on the first current path; and

a fourth current mirror located between the second current mirror and the output node on the first current path.

16. The circuit of claim 15 , wherein the gate dimensions of the transistors of the first mentioned current mirror and the second current mirror are larger than gate dimensions of the transistors of the third and fourth current mirrors.

17. A method comprising:

providing a current through a current path from a power supply node that includes a low-ohmic circuit and a load;

providing a current from the power supply node, through a reference transistor, to a ground voltage;

setting a current threshold level based on the current provided through the reference transistor and a ratio of a transconductance of the low-ohmic circuit to a transconductance of the reference transistor;

providing a current-sensing circuit, responsive to and sensing current through the low-ohmic circuit, having a normal state of operation and an over-current state of operation;

during the normal state of operation, sensing an amount of current passing through the low-ohmic circuit that is less than the current threshold level; and

during the over-current state of operation, sensing an amount of current passing through the low-ohmic circuit that is greater than the current threshold level.

18. The method of claim 17 , further including generating an output signal to indicate which state the current sensing circuit is in, wherein the output signal causes a breakage in a current path to the load.

19. The method of claim 17 , wherein setting a current threshold level includes:

generating a reference current;

scaling the current provided from the power supply through a reference transistor to the ground voltage according to the reference current to generate a reference voltage, the reference current being equal to the current threshold level scaled by a ratio of a transconductance of the low-ohmic circuit to a transconductance of the reference transistor.

Assignments (13)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 13, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 048328/0964 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2017
From: NEXPERIA B.V.
To: NXP B.V.
Reel/Frame 041002/0426 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2016
From: NXP B.V.
To: NEXPERIA B.V.
Reel/Frame 039610/0734 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 21, 2011
From: DONG, XIAORU; JANS, THIERRY; CHRISTIAANS, PETER
To: NXP B.V.
Reel/Frame 026943/0650 →