Circuit, system and method for controlling read latency
A read latency control circuit is described having a clock synchronization circuit and a read latency control circuit. The clock synchronization circuit includes an adjustable delay line to generate an output clock signal whose phase is synchronized with the phase of the input clock signal. The read latency control circuit captures a read command signal relative to the timing of the input clock signal and outputs the read command signal relative to the timing of the output clock signal such that the read command signal is outputted indicative of a specified read latency.
1. A latency control apparatus, comprising:
a synchronization circuit comprising:
a delay line configured to receive an input clock signal and delay the input clock signal by a delay amount to provide a delayed input clock signal; and
a feedback circuit coupled to the delay line and configured to receive the input clock signal and the delayed input clock signal, the feedback circuit further configured to provide a count signal responsive to achieving a locking, condition, the count signal indicative of a number of clock cycles used to achieve the locking condition between the input clock signal and the delayed input clock signal; and
a read latency control circuit configured to delay a read signal based, at least in part, on the delay amount.
2. The latency control apparatus of claim 1 , wherein the feedback circuit comprises a phase detector configured to adjust a timing of the input clock signal and provide the count signal.
3. The latency control apparatus of claim 2 , wherein the feedback circuit is further configured to delay the delayed input clock signal by an integer number of clock cycles responsive, at least in part, to adjusting the timing of the input clock signal.
4. The latency control apparatus of claim 1 , wherein the synchronization circuit further comprises:
an initialization circuit configured to prevent the delay line from toggling for a predetermined number of clock cycles responsive, at least in pan, to receipt of a signal from the feedback circuit.
5. The latency control apparatus of claim 1 , wherein the read latency control circuit is further configured to delay the read signal based, at least in part, on a match signal.
6. The latency control apparatus of claim 5 , further comprising:
a latch configured to capture the read signal based, at least in part, on the input clock signal.
7. The latency control apparatus of claim 1 , wherein the read latency control circuit is further configured to delay the read signal based, at least in part, on a latency signal received from a mode register.
8. A method of providing read data with a latency, comprising:
receiving an input clock signal;
delaying the input clock signal by a first amount to provide an internal clock signal;
providing a count signal responsive to achieving a phase-locked condition, the count signal based, at least in part, on the first amount and indicative of a number of clock cycles used to delay the input clock signal to achieve the phase-locked condition; and
delaying a read signal by a second amount based, at least in part, on the count signal.
9. The method of claim 8 , further comprising:
providing the read signal to an output driver based, at least in part, on the internal clock signal.
10. The method of claim 8 , wherein the second amount is based, at least in part, on a match signal.
11. The method of claim 8 , wherein said delaying the read signal comprises:
latching the read signal based, at least in part, on the input clock signal; and
providing a match signal based at least in part, on the internal clock signal.
12. The method of claim 8 , wherein the first amount is based, at least in part, on a delay of a delay line.
13. The method of claim 8 , further comprising:
before said providing a count signal, locking a delay line for a predetermined number of clock cycles.
14. The method of claim 8 , wherein the count signal represents a number of dock cycles.