IP Library Granted Patent US 8,853,013
Granted Patent B2
US 8,853,013 · App. 13/213,092 · Granted Oct 7, 2014

Method for fabricating field effect transistor with fin structure

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Quick Facts
Patent No.
US 8,853,013
App. No.
13/213,092
Granted
Oct 7, 2014
Kind
B2
Abstract

A method for fabricating a field effect transistor with fin structure includes the following sequences. First, a substrate is provided and at least a fin structure is formed on the substrate. Then, an etching process is performed to round at least an upper edge in the fin structure. Finally, a gate covering the fin structure is formed.

Claims (28)

1. A method for fabricating a field effect transistor with fin structure, comprising:

providing a substrate;

forming a patterned hard mask on the substrate;

transferring pattern of the patterned hard mask into the substrate to form at least a fin structure on the substrate;

after the step of forming the fin structure, performing an etching process to round at least an upper edge in the fin structure;

before the step of performing the etching process, pulling back the patterned hard mask to expose portions of a top surface of the fin structure from the patterned hard mask;

forming a gate covering the fin structure; and

forming a source and a drain at each side of the gate.

2. A method for fabricating a field effect transistor with fin structure according to claim 1 , wherein the substrate is a bulk silicon substrate or a silicon-on-insulator (SOI) substrate.

3. A method for fabricating a field effect transistor with fin structure according to claim 1 , wherein the step of pulling back the patterned hard mask comprises a wet etch process or plasma etch process.

4. A method for fabricating a field effect transistor with fin structure according to claim 1 , further comprising:

after the step of performing the etching process, forming at least an insulation layer on the substrate, wherein the insulation layer butted contacts the fin structure.

5. A method for fabricating a field effect transistor with fin structure according to claim 1 , wherein the fin structure comprises a silicon layer, silicon-germanium layer or a combination thereof.

6. A method for fabricating a field effect transistor with fin structure according to claim 1 , wherein the etching process etches at least a sidewall of the fin structure.

7. A method for fabricating a field effect transistor with fin structure, comprising:

providing a substrate;

forming at least a fin structure on the substrate having a patterned hard mask on a top surface of the substrate;

performing a pull back process to expose portions of a top surface of the fin structure from the patterned hard mask;

performing an etching process to round at least an upper edge in the fin structure;

removing the patterned hard mask;

forming a gate covering the fin structure; and

forming a source and a drain at each side of the gate.

8. A method for fabricating a field effect transistor with fin structure according to claim 7 , wherein the substrate comprises a bulk silicon substrate or silicon-on-insulator substrate.

9. A method for fabricating a field effect transistor with fin structure according to claim 7 , wherein the fin structure comprises a silicon layer, silicon-germanium layer or a combination thereof.

10. A method for fabricating a field effect transistor with fin structure according to claim 7 , wherein the pull back process comprises a wet etch process or plasma etch process.

11. A method for fabricating a field effect transistor with fin structure according to claim 7 , wherein the etching process can etch at least a sidewall of the fin structure.

12. A method for fabricating a field effect transistor with fin structure according to claim 7 , further comprising:

after the step of performing the etching process to round at least the upper edge in the fin structure, forming at least an insulation layer on the substrate, wherein the insulation layer contacts the fin structure.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 26, 2021
From: UNITED MICROELECTRONICS CORPORATION
To: MARLIN SEMICONDUCTOR LIMITED
Reel/Frame 056991/0292 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2011
From: TSAI, SHIH-HUNG; HUANG, RAI-MIN; LIN, CHIEN-TING
To: UNITED MICROELECTRONICS CORP.
Reel/Frame 026775/0080 →