Method and System of Using One-Time Programmable Memory as Multi-Time Programmable in Code Memory of Processors
A method, device and system of using an One-Time-Programmable (OTP) memory as an Multiple-Time Programming (MTP) memory equivalent is disclosed. The use of OTP memory in this manner allows code to be updated one or more times and yet remain small in size and relatively easy to process (fabricate). The code can be program code for a processor, such as boot code, boot code kernel or other instruction code. According to one aspect, an OTP memory is able to functionally operate as if it were a MTP memory through intelligent use of NOPs, which are no operations. Subsequently, if a particular subroutine or function in the program code needs to be modified, an instruction (e.g., JUMP instruction) can be programmed into the NOP so that certain existing instructions can be bypassed and the execution of instructions of a new module can be performed.
1 . An integrated circuit, comprising:
a processor;
a One-Time-Programmable (OTP) memory as a part or all of a memory operatively coupled to the processor; and
an instruction code for the processor, the instruction code being programmed into the OTP memory, and the instruction code having a plural of modules and at least one of the modules having at least one No-Operation (NOP) instruction,
wherein the at least one module having at least one NOP instruction being configured to be updated by programming a new module into an unused portion of the OTP memory and by programming a module-calling or branch instruction into the at least one NOP instruction to jump to a starting address of the new module or to a new target address upon execution.
2 . An integrated circuit as recited in claim 1 , wherein the instruction code for NOP in the processor is an instruction word of virgin states in the OTP memory.
3 . An integrated circuit as recited in claim 1 , wherein the at least one module having the at least one NOP instruction includes n NOPs so that the instruction code within the module is able to be re-programmed up to n times.
4 . An integrated circuit as recited in claim 3 , wherein the at least one module can be updated n times by repetitively programming a different module-calling or branch instruction into one of the n NOPs, starting with the last NOP to be executed in set of n consecutive NOP instructions.
5 . An integrated circuit as recited in claim 1 , wherein the new module contains at least one NOP instruction.
6 . An integrated circuit as recited in claim 1 , wherein the at least one module includes a group of instructions, a subroutine, or a function.
7 . An integrated circuit as recited in claim 1 , wherein the at least one module is within another module.
8 . An electronics system comprising:
a processor;
a One-Time-Programmable (OTP) memory as a part or all of a code memory operatively coupled to the processor; and
an instruction code for the processor, the instruction code being programmed into the OTP memory, and the instruction code having a plural of modules and at least one of the modules having at least one No-Operation (NOP) instruction,
wherein the at least one module having at least one NOP instruction being configured to be updated by programming a new module into an unused portion of the OTP memory and by programming a module-calling or branch instruction into the at least one NOP instruction to jump to a starting address of the new module or to a new target address upon execution.
9 . An electronics system as recited in claim 8 , wherein the instruction code for NOP in the processor is an instruction word of virgin states in the OTP.
10 . An electronics system as recited in claim 8 , wherein the module is inserted with n NOPs so that the NOP space can be re-programmed n times to modify some codes n times.
11 . An electronics system as recited in claim 10 , wherein the module can be updated n times by repetitively programming a call-to-new module or branch instruction into a NOP, starting with the last NOP executed in n consecutive NOP instructions.
12 . An electronics system as recited in claim 8 , wherein the new module contains at least one NOP instruction.
13 . An electronics system as recited in claim 8 , wherein the module is a group of instructions, subroutine, or function.
14 . An electronics system as recited in claim 8 , wherein the module is within another module.
15 . A method of providing an OTP memory configured to be updateable, the method comprising:
storing instruction code into the OTP memory, the instruction code to be executed by a processor operatively connect to the OTP memory, the instruction code having a plural of modules, and at least one of the modules having at least one No-Operation (NOP) instruction at a NOP location;
subsequently programming a new module into a previously unused portion of the OTP memory to stored additional instruction code to the OTP memory; and
programming a module-calling or branch instruction into the NOP location to subsequently direct program execution to the additional instruction code of the new module.
16 . A method as recited in claim 15 , wherein a branch or jump instruction is programmed at the NOP location to branch to a starting address of the new module.
17 . A method as recited in claim 15 , wherein a module call instruction is programmed at the NOP location to branch to a starting address of the new module.
18 . A method as recited in claim 15 , wherein the new module includes a group of instructions, a subroutine or a function.
19 . A method as recited in claim 15 , wherein the new module is within another module.
20 . A non-transitory computer readable medium including at least computer program code stored thereon for programming an OTP memory configured to be updateable, the computer readable medium comprising:
computer program code for storing instruction code into the OTP memory, the instruction code stored being to be executable by a processor operatively connect to the OTP memory, the instruction code having a plural of modules, and at least one of the modules having at least one No-Operation (NOP) instruction at a NOP location;
computer program code for subsequently programming a new module into a previously unused portion of the OTP memory to stored additional instruction code to the OTP memory; and
computer program code for programming an instruction into the NOP location to subsequently redirect program execution to the additional instruction code of the new module.