Semiconductor devices and methods of fabricating the same

1. A method of fabricating a semiconductor memory device, the method comprising:

forming a mold stack on a substrate, the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate;

forming a plurality of vertical channels that penetrate the mold stack and that contact the substrate;

patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate;

removing one of the first and second sacrificial layers to form recessed regions in the mold stack;

forming gates in the recessed regions;

forming a data storage layer, at least a portion of the data storage layer being formed between the vertical channels and the gates;

forming air gaps between the gates by removing the other of the first and second sacrificial layers; and

forming an insulation layer in the word line cuts.

2. The method as claimed in claim 1 , wherein:

the first sacrificial layers are formed of silicon germanium layers, and

the second sacrificial layers are formed of silicon nitride layers.

3. The method as claimed in claim 2 , wherein:

the recessed regions are formed by removing the second sacrificial layers using a first etchant supplied through the word line cuts, and

the gates are formed by filling the recessed regions with a conductive material.

4. The method as claimed in claim 3 , wherein the air gaps are formed by removing the first sacrificial layers using a second etchant supplied through the word line cuts.

5. The method as claimed in claim 3 , wherein forming the data storage layer includes sequentially forming a tunneling insulation layer, a trapping insulation layer, and a blocking insulation layer in the recessed regions before forming the gates therein or on sidewalls of vertical channel holes before forming the vertical channels therein.

6. The method as claimed in claim 3 , wherein forming the data storage layer includes:

forming a tunneling insulation layer on sidewalls of vertical channel holes before forming the vertical channels therein,

forming a blocking insulation layer in the recessed regions before forming the gates therein, and

forming a trapping insulation layer, the trapping insulation layer being formed on the tunneling insulation layer after forming the tunneling insulation layer on the sidewalls of the vertical channel holes or the trapping insulation layer being formed in the recessed regions before forming the blocking insulation layer in the recessed regions.

7. The method as claimed in claim 1 , wherein forming the insulation layer includes depositing an insulating material with a physical vapor deposition technique to contact the substrate.

8. The method as claimed in claim 1 , further comprising:

forming a plurality of vertical channel holes that penetrate the mold stack and expose the substrate, and

oxidizing the first sacrificial layers exposed by the vertical channel holes to form a plurality of sacrificial oxide layers prior to forming the vertical channels in the vertical channel holes.

9. The method as claimed in claim 1 , further comprising forming a capping insulation layer on the mold stack.

10. The method as claimed in claim 9 , wherein:

patterning the mold stack to form the word line cuts includes patterning the capping insulation layer,

forming an insulation layer pattern which includes forming overhanging portions that overhang ends of the capping insulation layer adjacent to the word line cuts, and

the insulation layer pattern being spaced apart from the substrate and closing upper openings of the word line cuts.

11. The method as claimed in claim 1 , further comprising forming a protection layer on sidewalls of the vertical channels exposed by the air gaps.

12. A method of fabricating a semiconductor memory device, the method comprising:

forming a mold stack on a substrate, the mold stack including first sacrificial layers and second sacrificial layers alternately stacked on the substrate;

forming a plurality of vertical channels that penetrate the mold stack;

patterning the mold stack to form word line cuts between the vertical channels, the word line cuts exposing the substrate;

removing one of the first and second sacrificial layers to form recessed regions in the mold stack;

filling a conductive material in the recessed regions;

forming air gaps between the recessed regions filled with the conductive material by removing the other of the first and second sacrificial layers; and

forming an insulation layer in the word line cuts to close the word line cuts, at least a portion of the word line cuts between an uppermost layer of the mold stack and the substrate being unfilled with the insulation layer.

13. The method as claimed in claim 12 , wherein filling the conductive material in the recessed regions includes forming gates such that adjacent gates are spaced apart by one of the air gaps, the insulation layer, and a void in the word line cuts.

14. The method as claimed in claim 12 , wherein forming the insulation layer includes having the air gaps between the insulation layer and the vertical channels.

15. The method as claimed in claim 14 , wherein the insulation layer leaves voids within the word line cuts.

16. The method as claimed in claim 12 , wherein, when closing the word line cuts, the insulation layer is spaced apart from the substrate to form the unfilled portions of the word line cuts and the air gaps are continuous with unfilled portions of the word line cuts.