Wafer, crystal growth method, and semiconductor device
View Patent ↗According to one embodiment, a wafer includes a substrate, a base layer, a foundation layer, an intermediate layer and a functional unit. The substrate has a major surface. The base layer is provided on the major surface and includes a silicon compound. The foundation layer is provided on the base layer and includes GaN. The intermediate layer is provided on the foundation layer and includes a layer including AlN. The functional unit is provided on the intermediate layer and includes a nitride semiconductor. The foundation layer has a first region on a side of the base layer, and a second region on a side of the intermediate layer. A concentration of silicon atoms in the first region is higher than a concentration of silicon atoms in the second region. The foundation layer has a plurality of voids provided in the first region.
1. A wafer comprising:
a substrate having a flat major surface;
a base layer provided on the major surface and including a silicon compound;
a foundation layer provided on the base layer and including GaN;
an intermediate layer provided on the foundation layer and including a layer including AlN; and
a functional unit provided on the intermediate layer and including a nitride semiconductor,
the foundation layer including a first region, and a second region provided between the first region and the intermediate layer,
a concentration of silicon atoms in the first region being higher than a concentration of silicon atoms in the second region, and
the foundation layer having a plurality of voids provided in the first region.
2. The wafer according to claim 1 , further comprising a third region provided between the base layer and the foundation layer, the third region contacting the foundation layer, the third region including silicon and having a thickness not less than 1 nanometer and not more than 50 nanometers.
3. The wafer according to claim 1 , wherein a thickness of the foundation layer is not less than 50 nanometers and not more than 1500 nanometers.
4. The wafer according to claim 1 , wherein the foundation layer has a minute gap extending along a stacked axis in a direction from the foundation layer toward the functional unit.
5. The wafer according to claim 4 , wherein at least a part of the minute gap is provided in the second region.
6. The wafer according to claim 1 , wherein
the intermediate layer includes a plurality of first layers including a nitride semiconductor, and a second layer provided between the first layers and including a nitride semiconductor, and
the second layer has at least one of a lattice spacing different from a lattice spacing in the first layer, and a thermal expansion coefficient different from a thermal expansion coefficient in the first layer.
7. The wafer according to claim 1 , wherein the intermediate layer includes a plurality of first layers including AlN, and a second layer provided between the first layers and including GaN.
8. A semiconductor device, comprising:
a foundation layer including GaN;
a functional unit including a nitride semiconductor;
an intermediate layer provided between the foundation layer and the functional unit and including a layer including AlN;
a base layer including a silicon compound, the foundation layer being disposed between the base layer and the intermediate layer, the base layer being flat;
the foundation layer having a first region and a second region provided between the first region and the intermediate layer,
a concentration of silicon atoms in the first region being higher than a concentration of silicon atoms in the second region, and
a first surface on a side opposite to the intermediate layer of the foundation layer having a plurality of concave portions.
9. The device according to claim 8 , further comprising a base layer contacting the first surface and including a silicon compound.
10. The device according to claim 8 , further comprising:
a third region provided between the base layer and the foundation layer, the third region contacting the foundation layer, the third region including silicon and having a thickness not less than 1 nanometer and not more than 50 nanometers.
11. The device according to claim 8 , wherein
the intermediate layer includes a plurality of first layer including a nitride semiconductor, and a second layer provided between the first layers and including a nitride semiconductor, and
the second layer has at least one of a lattice spacing different from a lattice spacing in the first layer, and a thermal expansion coefficient different from a thermal expansion coefficient in the first layer.
12. The device according to claim 9 , wherein the concave portions form a void provided between the foundation layer and the base layer.
13. The device according to claim 8 , wherein a thickness of the foundation layer is not less than 50 nanometers and not more than 1500 nanometers.
14. The wafer according to claim 2 , wherein the silicon layer has a (111) plane.
15. The wafer according to claim 2 , wherein the silicon layer has a portion oriented in a direction of the (111) plane.
16. The wafer according to claim 4 , wherein the foundation layer includes a plurality of voids.
17. The device according to claim 10 , wherein the silicon layer has a (111) plane.
18. The device according to claim 10 , wherein the silicon layer has a portion oriented in a direction of the (111) plane.
19. The device according to claim 9 , further comprising a substrate having a major surface, wherein the base layer is provided on the major surface, and the foundation layer is provided on the base layer.
20. The device according to claim 8 , wherein the foundation layer includes a minute gap extending along a stacked axis in a direction from the foundation layer toward the functional unit.
21. The device according to claim 20 , wherein at least a part of the minute gap is provided in the second region.
22. A wafer comprising:
a substrate having a major surface;
a base layer provided on the major surface and including a silicon compound;
a foundation layer provided on the base layer and including GaN, the foundation layer including a first region and a second region;
an intermediate layer provided on the foundation layer and including a layer including AlN;
a functional unit provided on the intermediate layer and including a nitride semiconductor; and
a third region provided between the base layer and the foundation layer, the third region contacting the foundation layer, the third region including silicon and having a thickness not less than 1 nanometer and not more than 50 nanometers,
the second region provided between the first region and the intermediate layer,
a concentration of silicon atoms in the first region being higher than a concentration of silicon atoms in the second region, and
the foundation layer having a plurality of voids provided in the first region.
23. A semiconductor device, comprising:
a foundation layer including GaN, the foundation layer including a first region and a second region;
a functional unit including a nitride semiconductor;
an intermediate layer provided between the foundation layer and the functional unit and including a layer including AlN;
a base layer including a silicon compound, the foundation layer being disposed between the base layer and the intermediate layer; and
a third region provided between the base layer and the foundation layer, the third region contacting the base layer and the foundation layer, the third region including silicon and having a thickness not less than 1 nanometer and not more than 50 nanometers,
the second region provided between the first region and the intermediate layer,
a concentration of silicon atoms in the first region being higher than a concentration of silicon atoms in the second region, and
a first surface on a side opposite to the intermediate layer of the foundation layer having a plurality of concave portions.