Composite analog-to-digital converter

1. An analog-to-digital converter (ADC) comprising:

a plurality of single slope ADCs, each comprising:

an analog input operable to receive an analog input signal;

a ramp input operable to receive an analog ramp signal of a plurality of analog ramp signals; and

a comparator operable to compare the analog input signal to the analog ramp signal; and

an output operable to produce a digital representation of the analog input signal based upon the comparison, wherein the plurality of single slope ADCs are operable to receive analog ramp signals that are out of phase with one other;

a ramp generator that is operable to generate analog ramp signals for the plurality of single slope ADCs, the ramp generator comprising circuitry to simultaneously generate the plurality of analog ramp signals such that successive ramps signals of the plurality of analog ramp signals are out of phase with one another based upon a clock signal; and

digital output circuitry operable to receive outputs from the plurality of single slope ADCs and to produce a digital representation of the analog input signal based thereupon.

2. The ADC of claim 1 , wherein the plurality of single slope ADCs are operable to receive a succession of time corresponding analog ramp signals that are spaced apart temporally, the time corresponding analog ramp signals received at successive single slope ADCs in a cyclic fashion, such the single slope ADCs provides a digital representation of the analog input signal input using the time corresponding analog ramp signals.

3. The ADC of claim 2 , wherein of the plurality of single slope ADCs are operable to receive the analog input signal over time in a cyclic fashion.

4. The ADC of claim 1 , wherein:

the plurality of single slope ADCs comprise four single slope ADCs; and

the four single slope ADCs are operable such that at any time of operation:

a first single slope ADC is in a reset mode;

a second single slope ADC is receiving the analog input signal;

a third single slope ADC is converting the analog input signal to a corresponding digital representation; and

a fourth single slope ADC is conveying a digital representation of yet another of one of the analog input signals.

5. The ADC of claim 1 , wherein the ramp generator comprises:

a first circuit for generating a plurality of first analog ramp signals; and

a plurality of second circuits, the plurality of second circuits respective to the plurality of single slope ADCs and operable to produce the plurality of analog ramp signals based upon the plurality of first analog ramp signals.

6. The ADC of claim 5 , wherein the first circuit of the ramp generator is operable to produce a plurality of first analog ramp signals that are all out of phase with one another, and such that successive first analog ramp signals are out of phase by a single clock period.

7. The ADC of claim 5 , wherein:

the first analog ramp signals comprise coarse ramp signals; and

the second analog ramp signals comprise fine ramp signals.

8. The ADC of claim 1 , wherein the ramp generator comprises:

a plurality of resistive elements arranged in series so as to form a ring;

a switch network;

first and second power supplies, producing outputs at different levels; and

a controller arranged to control the switch network so as to connect a first power supply successively to nodes of the resistor ring while also connecting a second power supply to a node diametrically opposite the node to which the first power supply is connected, such that the first and second supplies are always connected to diametrically opposed nodes and such that first and second power supply connections effectively rotate around the ring during ramp generation, thereby providing a plurality of ramp outputs, from different nodes of the resistor ring.

9. The ADC of claim 8 , wherein the resistor ring is comprised of four times as many resistors as ramp outputs, the ramp outputs being taken from two diametrically opposed nodes multiplexed together.

10. The ADC of claim 8 , wherein the ramp generator comprises two switches for some of the nodes, so as to enable selective connection of the nodes to the power supplies.

11. The ADC of claim 1 , wherein single slope ADCs comprises sample and hold circuits that are operative to sample the analog input signal and to maintain a voltage of the sampled analog input signal during conversion to a corresponding digital representation.

12. The ADC of claim 11 , wherein the sample and hold circuits comprise single pole single throw switches in series with capacitors, the switches being operative to couple the analog input signals to the capacitors for storage thereon.

13. The ADC of claim 1 , wherein the single slope ADCs comprise comparators that are operative to receive an analog input signal at a first input and an analog ramp signal at a second input.

14. The ADC of claim 1 , wherein the single slope ADCs comprise a differential sample and hold circuit configured to sample one end of a differential input signal onto a first input of a comparator, and the other end of the differential input signal onto a second input of the comparator and then to apply two ramp signals of opposite slope such that one is applied to each input, the comparator output being operable to flip when its inputs reach a common level, the time taken to do so being determined by the differential input signal.

15. The ADC of claim 1 , further comprising a digital counter, wherein the plurality of single slope ADCs comprises a digital memory coupled to the digital counter such that the digital counter is operative to cycle continuously and the ADCs are configured to convey a value from the digital counter to the digital memories, the ADC being further operable to read a final value from each digital memory, the final value being dependent upon the analog input signal of the corresponding single slope ADC.

16. The ADC of claim 15 , wherein the ADC is operable to convert values conveyed from the digital counter to a coded value according to a code in which two successive values differ in respect of only one bit, such as Gray code.

17. The ADC of claim 1 , wherein the analog ramp signals received by at least some of the single slope ADCs covers only a sub-range within the total possible range of the ADC.

18. The ADC of claim 1 , wherein the analog ramp signals received by each of the single slope ADCs covers only a sub-range within the total possible range of the ADC.

19. The ADC of claim 18 , wherein a number of the single slope ADCs operate in parallel to convert a single analog input signal, the number of single slope ADCS being operable to receive an analog ramp signal that covers only a sub-range within the total possible range of the analog input signal, the sub-ranges together covering the total possible range.

20. A method of analog-to-digital conversion comprising:

receiving an analog input signal and respective analog ramp signals at a plurality of single slope analog-to-digital converters (ADCs), such that successive ramps signals are out of phase with one another based upon a clock signal; and

operating the plurality of single slope ADCs to provide digital representations of the analog input signal in dependence on the analog input signal and the respective analog ramp signals; and

combining the digital representations produced by the plurality of single slope ADCs to produce a composite output.

21. The method of claim 20 further comprising receiving a succession of analog input signals and a succession of time corresponding analog ramp signals, the analog input signals and time corresponding analog ramp signals being spaced apart temporally, the analog input signals and corresponding analog ramp signal being received at successive single slope ADCs in a cyclic fashion, such that the single slope ADCs provide a digital representation of the analog input signal input thereto using the time corresponding analog ramp signal.

22. The method of claim 21 , wherein, at any one time, a first single slope ADC is in a reset mode, a second single slope ADC is receiving one of the analog input signal, a third single slope ADC is converting another of the analog input signal to a corresponding digital representation and a fourth single slope ADC is conveying a digital representation of yet another of the analog input signals.

23. The method of claim 22 , further comprising generating analog ramp signals for the plurality of single slope ADCs using a single ramp generator, such that the plurality of ramp signals are all out of phase with one other, and such that successive ramps signals are out of phase by a single clock period.