IP Library Granted Patent US 8,402,197
Granted Patent B2
US 8,402,197 · App. 13/215,011 · Granted Mar 19, 2013

Multi-port system and method for routing a data element within an interconnection fabric

Inventors: Lynne M. Brocco (Cambridge, MA); Todd R. Comins (Chelmsford, MA); Nathan J. Dohm (Natick, MA); David E. Mayhew (Northborough, MA); Carey J. McMaster (Stow, MA)
Assignee: Jinsalas Solutions, LLC
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Quick Facts
Patent No.
US 8,402,197
App. No.
13/215,011
Granted
Mar 19, 2013
Kind
B2
Abstract

A method and structure(s) for providing a data path between and among nodes and processing elements within an interconnection fabric are described. More specifically, a device comprising a first circuit configured to couple between a first bus and a link is described. The circuit may be configured to operate as a bridge, support PCI configuration cycles, send outgoing information serially through the link in a format different from that of the first bus, and allow a host processor, communicating through the first bus, to selectively address one or more remote devices to which the device is configured to allow access. In some embodiments, the first circuit may support “spoof-proof” data protocols, and the device may operate in multiple modes including root bridge, leaf bridge, and gateway mode. Multiple addressing models may also be used.

Claims (38)

1. A device, comprising:

a first circuit configured to couple between a first bus and a link;

wherein the device is configured to allow access by a host processor to a remote device;

wherein the first circuit is configured to operate as a bridge, support PCI Type 0 and Type 1 configuration cycles, send outgoing information serially through the link in a format different from a format supported by the first bus, and allow the host processor to selectively address the remote device by communicating through the first bus.

2. The device of claim 1 , wherein the first circuit is configured to transport data from the host processor to the remote device according to a first protocol, wherein data transported by the first circuit and arriving at the remote device in accordance with the first protocol is guaranteed to have been provided by a source indicated by the first protocol.

3. The device of claim 2 , wherein the first protocol is a turn-based protocol.

4. The device of claim 1 , wherein the device is configured to receive address information from the host processor that assigns a unique address range to the remote device; and

wherein the first circuit comprises a storage element configured to store the received address information.

5. The device of claim 4 , wherein the received address information is included as part of at least one of a PCI Type 0 configuration cycle and a PCI Type 1 configuration cycle.

6. The device of claim 1 , wherein the device comprises a receiver unit configured to decode clock values embedded in a serial data stream.

7. The device of claim 1 , wherein the link is configured to couple to a switch, and wherein the device is configured to convert between data in a bus format and data in a network format with which the switch is compatible.

8. The device of claim 1 , wherein the device is configured to operate in a root bridge mode, a leaf bridge mode, and a gateway mode.

9. The device of claim 1 , wherein the device is configured to convert Ethernet packets into Data Transmission Protocol frames using address mapping.

10. The device of claim 1 , wherein the device is configured to provide the outgoing information to a serial bus.

11. The device of claim 1 , wherein the first bus is a parallel bus.

12. The device of claim 1 , wherein a format of the outgoing information includes serial data and the format supported by the first bus includes parallel data.

13. The device of claim 1 , wherein the first bus is a kind of PCI bus.

14. The device of claim 1 , wherein the device further comprises a second circuit configured to couple between the link and a second bus, wherein the remote device is configured to couple to the second bus, wherein the second circuit is configured to operate as a bridge and is configured to support PCI Type 0 and Type 1 configuration cycles.

15. A system, comprising:

a fabric including one or more switches, wherein a first switch of the one or more switches has a plurality of ports; and

a first circuit configured to couple between a first port of the first switch and a first bus; wherein the first circuit is configured to operate as a bridge, support PCI Type 0 and Type 1 configuration cycles, send information via the fabric in a format different from a format supported by the first bus, and allow a host processor to selectively address a remote device via the bus.

16. The system of claim 15 , wherein in a first mode of at least two modes, the first circuit is configured to convert communications received in a first format to either one of a second and a third format, and to convert communications received in either one of the second and third formats to the first format.

17. The system of claim 16 , wherein in a second of the at least two modes, the first circuit is configured to convert communications received in the first format to the second format but not the third format, and to convert communications received in the second format to the first format, but not convert communications received in the third format to the first format.

18. The system of claim 15 , wherein the first circuit is configured to transport data from the host processor to the remote device according to a first protocol, wherein data transported by the first circuit and arriving at the remote device in accordance with the first protocol is guaranteed to have been provided by a source indicated by the first protocol.

19. The system of claim 18 , wherein the first protocol is a turn-based routing protocol.

20. The system of claim 15 , wherein a device including the first circuit includes one or more configuration registers, is configured as operate in a root bridge mode or a leaf bridge mode, and is configured to convert network packets into bus packets using address mapping;

wherein the device including the first circuit includes a plurality of different mechanisms to control access to and from secondary bus devices during operation in leaf bridge mode.

21. The system of claim 15 , wherein a device including the first circuit is configured to operate in a root bridge mode, a leaf bridge mode, and a gateway mode.

22. A switch, comprising:

a plurality of ports; and

a first storage element configured to implement a PCI configuration space;

wherein the switch is configured to couple between a first circuit and a remote device, wherein the first circuit is configured to communicate with a host processor coupled to a first bus, operate as a bridge, support PCI Type 0 and Type 1 configuration cycles, and send outgoing information in a format different from a format supported by the first bus;

wherein the remote device is configured to respond to PCI configuration cycles originating from the processor; and

wherein the switch is configured to respond to the PCI configuration cycles originating from the processor, operate as a bridge, support PCI Type 0 and Type 1 configuration cycles, and perform address translation on packets received via the plurality of ports.

23. The switch of claim 22 , wherein the switch is configured to support three or more addressing models, and wherein the switch is configured to appear as a PCI-to-PCI bridge to configuration software in a first of the three or more addressing models.

24. The switch of claim 22 , wherein each of the plurality of ports of the switch is associated with a corresponding one of a plurality of turn values.

25. The switch of claim 22 , wherein the switch is configured to alter path specifications for packets received via the plurality of ports.

26. The switch of claim 22 , wherein the switch is configured to couple to a second circuit, wherein the second circuit is configured to couple to a second bus, operate as a bridge and support PCI Type 0 and Type 1 configuration cycles.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2019
From: INTELLECTUAL VENTURES ASSETS
To: SAMSUNG ELECTRONCS CO., LTD.
Reel/Frame 049266/0532 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 14, 2019
From: CALLAHAN CELLULAR L.L.C.
To: INTELLECTUAL VENTURES ASSETS 124 LLC
Reel/Frame 049167/0403 →
MERGER Recorded Jan 12, 2016
From: JINSALAS SOLUTIONS, LLC
To: CALLAHAN CELLULAR L.L.C.
Reel/Frame 037487/0249 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2011
From: DOLPHIN INTERCONNECT SOLUTIONS ASA
To: JINSALAS SOLUTIONS, LLC
Reel/Frame 026831/0968 →
Continuity (5)
Continuation 12643385 · Dec 21, 2009
Continuation 10945633 · Sep 21, 2004
Division 10152656 · May 21, 2002
Provisional Application 60330215 · Oct 17, 2001
Related Publication 20120131255A1 · May 24, 2012