Fractional frequency divider
An oscillator may output phased signals to a phase interpolator which is to generate an adjustable output clock signal having a phase offset relative to at least one of the phased signals received from the oscillator. A divider may then divide the frequency of the output signal generated by the phase interpolator by an integer factor.
1. A system, comprising:
an oscillator to output phased signals;
a phase interpolator to:
receive the phased signals output by the oscillator,
generate an adjustable output clock signal having a phase offset relative to at least one of the phased signals received from the oscillator;
receive a control signal to digitally control the generation of the adjustable output clock signal, the control signal being a digital signal set at a digital 1 or a digital 0, the control signal is to control the phase interpolator so that the phase offset relative to the at least one phased signals received from the oscillator is a predetermined fractional amount of a period of the oscillator every clock cycle of an output of the divider; and
a divider to divide the frequency of the output clock signal generated by the phase interpolator by an integer factor, the divider to receive a dynamically adjustable control signal to vary a division range of the divider.
2. The system according to claim 1 , wherein the adjustable output signal has a same frequency as at least one of the phased signals received from the oscillator.
3. The system according to claim 1 , wherein the adjustable output clock signal is adjustable in accordance with (2^N b ) phase positions, wherein further N b corresponds to a number of control bits in the phase interpolator.
4. The system according to claim 1 , wherein the phase offset is advancing.
5. The system according to claim 1 , wherein the phase offset is lagging.
6. The system according to claim 1 , wherein the control signal is dynamically changed according to external settings.
7. The system according to claim 6 , wherein the control signal is output by a control engine.
8. The system according to claim 6 , wherein the control signal is output by a delta sigma modulator.
9. The system according to claim 1 , wherein a frequency of the control signal is the divided frequency output by the divider, or the frequency of the control signal is another frequency associated with the system.
10. A method, comprising:
generating a phased signal;
interpolating, based on a digital control signal set at a digital 1 or a digital 0, the phased signal to generate an adjustable output clock signal having a phase offset relative to the phased signal, the digital control signal is to control the interpolating so that the phase offset relative to the phased signal is a predetermined fractional amount of a period of the phase signal every clock cycle of the divided adjustable output clock signal; and
dividing the frequency of the adjustable output clock signal by an integer factor, the dividing controlled by an adjustable control signal to vary the integer value.
11. The method according to claim 10 , wherein the adjustable output clock signal has a same frequency as the phased signal.
12. The method according to claim 10 , wherein the adjustable output clock signal is adjustable in accordance with (2^N b ) phase positions, wherein further N b corresponds to a number of control bits in the phase interpolator.
13. The method according to claim 10 , wherein the phase offset is advancing or lagging.
14. The system according to claim 10 , wherein the control signal is dynamically changed according to external settings.
15. The method according to claim 10 , wherein a frequency of the control signal is the divided frequency, or the frequency of the control signal is another frequency associated with the system.
16. The method according to claim 10 , wherein the control signal is output by a control engine.
17. The method according to claim 10 , wherein the control signal is output by a delta sigma modulator.