Resistor and manufacturing method thereof
View Patent ↗A method for forming a resistor integrated with a transistor having metal gate includes providing a substrate having a transistor region and a resistor region defined thereon, forming a transistor having a polysilicon dummy gate in the transistor region and a polysilicon main portion with two doped regions positioned at two opposite ends in the resistor region, performing an etching process to remove the polysilicon dummy gate to form a first trench and remove portions of the doped regions to form two second trenches, and forming a metal gate in the first trench to form a transistor having the metal gate and metal structures respectively in the second trenches to form a resistor.
1. A resistor comprising:
a substrate;
a polysilicon main portion formed on the substrate;
two metal portions respectively positioned at two opposite ends of the polysilicon main portion on the substrate, wherein the metal portions respectively contact a spacer; and
two doped polysilicon regions respectively formed between the metal portions and the polysilicon main portion on the substrate, wherein the doped polysilicon regions contact both of the metal portions and the polysilicon main portion, and the doped polysilicon regions are spaced apart from the spacer by the metal portions.
2. The resistor according to claim 1 , further comprising a high-k dielectric layer and a bottom barrier layer sequentially formed on the substrate.
3. The resistor according to claim 2 , wherein the high-k dielectric layer and the bottom barrier layer are formed between the substrate and the polysilicon main portion, between the substrate and the metal portion, and between the substrate and the doped polysilicon region.
4. The resistor according to claim 2 , wherein the high-k dielectric layer and the bottom barrier layer are sandwiched between the metal portion and the doped polysilicon region.
5. The resistor according to claim 4 , wherein the doped polysilicon region is an L-shaped region.
6. The resistor according to claim 2 , wherein topmost portions of the high-k dielectric layer and the bottom barrier layer are lower than a surface of the metal portion.
7. The resistor according to claim 1 , wherein a width of the doped polysilicon region is defined depending on a required resistance.
8. The resistor according to claim 1 further comprising contacts electrically connecting to the metal portions, respectively.