Memory cell supply voltage control based on error detection

1. An apparatus comprising:

a memory circuitry including memory cells in columns, the memory circuitry to receive first and second power supply voltages, wherein the first power supply voltage is higher than the second power supply voltage;

an error detection circuitry to detect error in data stored by the memory cells of the memory circuitry; and

a supply voltage control circuitry operable to:

provide the first power supply voltage for those columns of memory cells of the memory circuitry that are associated with the detected error,

provide the second power supply voltage for those columns of memory cells that store error free data; and

provide, after reset or after power UP, the first power supply voltage again for those columns of memory cells of the memory circuitry that are associated with the detected error.

2. The apparatus of claim 1 , wherein the supply voltage control circuitry is to provide the first supply voltage for a predetermined subset of memory cells that include one or more memory cells having error.

3. The apparatus of claim 1 , wherein the memory circuitry includes access control circuitry to identify accessed memory cells and the supply voltage control circuitry is to provide the first supply voltage for one or more accessed memory cells.

4. The apparatus of claim 1 , wherein the supply voltage control circuitry is to switch to the first supply voltage for one or more memory cells to a greater voltage than the voltage of the second power supply.

5. The apparatus of claim 4 , comprising charge pump circuitry to generate the greater voltage.

6. The apparatus of claim 1 , wherein the error detection circuitry is to generate error detection data for data to be written to memory cells of the memory circuitry and is to use error detection data to detect error.

7. The apparatus of claim 1 , wherein the error detection circuitry is to use error detection data stored by memory cells of the memory circuitry in association with data read from memory cells of the memory circuitry to detect error in the read data.

8. The apparatus of claim 1 , wherein the error detection circuitry is to correct detected error.

9. The apparatus of claim 1 , wherein the error detection circuitry is to use error correction code.

10. The apparatus of claim 1 , wherein the memory cells include one or more static random access memory cells.

11. An apparatus comprising:

means for detecting error in data stored by columns of memory cells in columns, the memory cells to receive first and second power supply voltages, wherein the first power supply voltage is higher than the second power supply voltage;

means for providing the first power supply voltage for the columns of memory cells that are associated with the detected error;

means for providing the second power supply voltage for the columns of memory cells that store error free data; and

means for providing, after reset or after power up, the first power supply voltage again for those columns of memory cells of the memory circuitry that are associated with the detected error.

12. The apparatus of claim 11 , wherein the means for providing the first supply voltage includes means for increasing supply voltage for a predetermined subset of memory cells that include one or more memory cells having error.

13. The apparatus of claim 11 , comprising means for correcting detected error.

14. A method comprising:

detecting error in data stored by memory cells in columns, the memory cells to receive first and second power supply voltages, wherein the first power supply voltage is higher than the second power supply voltage;

providing the first power supply voltage for the columns of the memory cells that are associated with the detected error;

providing the second power supply voltage for the columns of the memory cells that store error free data; and

providing, after reset or after power up, the first power supply voltage again for those columns of memory cells of the memory circuitry that are associated with the detected error.

15. The method of claim 14 , wherein the the first power supply includes increasing supply voltage for a predetermined subset of memory cells that include one or more memory cells having error.

16. The method of claim 14 , comprising identifying accessed memory cells;

wherein the providing the first power supply includes increasing supply voltage for one or more accessed memory cells.

17. The method of claim 14 , wherein the providing the first power supply includes switching supply voltage for one or more memory cells to a greater voltage.

18. The method of claim 14 , comprising generating error detection data for data to be written to memory cells;

wherein the detecting error includes using error detection data.

19. The method of claim 14 , comprising correcting detected error.

20. A system comprising:

a volatile memory; and

a processor including:

a cache memory, the cache memory including memory circuitry including those columns of memory cells, the memory circuitry to receive first and second power supply voltages, wherein the first power supply voltage is higher than the second power supply voltage;

an error detection circuitry to detect error in data stored by the memory cells of the memory circuitry; and

a supply voltage control circuitry to:

provide the first power supply voltage for those columns of memory cells of the memory circuitry that are associated with the detected error,

provide the second power supply voltage the columns of memory cells that store error free data; and

provide, after reset or after power up, the first power supply voltage again for those columns of memory cells of the memory circuitry that are associated with the detected error.

21. The system of claim 20 , wherein the supply voltage control circuitry is to provide the first power supply voltage for a predetermined subset of memory cells that include one or more memory cells having error.

22. The system of claim 20 , wherein the error detection circuitry is to correct detected error.