Quaternary content addressable memory cell having one transistor pull-down stack
View Patent ↗Quaternary CAM cells are provided that include a compare circuit having a discharge path between a match line and ground potential, the single discharge path consisting essentially of a single transistor. In an embodiment, the single transistor has a gate coupled to a pull-down node and the compare circuit includes first and second gating transistors connected in series between the pull-down node and a ground potential, the first gating transistor having a gate to receive a comparand bit, and the second gating transistor having a gate to receive a complemented comparand bit.
1. A quaternary content addressable memory (CAM) cell for storing a data value having one of four possible states represented by first and second data bits, the CAM cell comprising:
first and second memory cells for storing the first and second data bits, respectively;
a first match line; and
a first compare circuit coupled to the first and second memory cells and having a single discharge path between the first match line and ground potential, the single discharge path consisting essentially of a single transistor, wherein the single transistor has a gate coupled to a pull-down node, and the first compare circuit further comprises:
first and second gating transistors connected in series between the pull-down node and ground potential, the first gating transistor having a gate to receive a comparand bit, and the second gating transistor having a gate to receive a complemented comparand bit.
2. The CAM cell of claim 1 , wherein the first compare circuit further comprises:
a first pass transistor coupled between the second memory cell and the pull-down node, and having a gate to receive the complemented comparand bit; and
a second pass transistor coupled between the first memory cell and the pull-down node, and having a gate to receive the comparand bit.
3. The CAM cell of claim 2 , wherein the first and second gating transistors are NMOS transistors, and the first and second pass transistors are PMOS transistors.
4. A quaternary content addressable memory (CAM) cell for storing a data value having one of four possible states represented by first and second data bits, the CAM cell comprising:
first and second memory cells for storing the first and second data bits, respectively;
a first match line; and
a first compare circuit coupled to the first and second memory cells and having a single discharge path between the first match line and ground potential, the single discharge path consisting essentially of a single transistor, wherein the single transistor has a gate coupled to a pull-down node, and the first compare circuit further comprises:
a first pass transistor coupled between the first memory cell and the pull-down node, and having a gate to receive a comparand bit;
a second pass transistor coupled between the second memory cell and the pull-down node, and having a gate to receive a complemented comparand bit; and
a single gating transistor coupled between the pull-down node and ground potential, and having a gate responsive to a logical combination of the comparand bit and the complemented comparand bit.
5. The CAM cell of claim 4 , wherein the gating transistor is an NMOS transistor, and the first and second pass transistors are PMOS transistors.
6. The CAM cell of claim 4 , wherein the logical combination comprises a logical AND function.
7. The CAM cell of claim 4 , wherein the gate of the gating transistor is coupled to a comparand signal gating line.
8. A quaternary content addressable memory (CAM) cell for storing a data value having one of four possible states represented by first and second data bits, the CAM cell comprising:
first and second memory cells for storing the first and second data bits, respectively;
a first match line; and
a first compare circuit coupled to the first and second memory cells and having a single discharge path between the first match line and ground potential, the single discharge path consisting essentially of a single transistor, wherein the single transistor has a gate coupled to a pull-down node, and the first compare circuit further comprises:
a first pass transistor coupled between the second memory cell and the pull-down node, and having a gate to receive a comparand bit;
a second pass transistor coupled between the first memory cell and the pull-down node, and having a gate to receive a complemented comparand bit; and
a single gating transistor coupled between the pull-down node and ground potential, and having a gate responsive to a logical combination of the comparand bit and the complemented comparand bit.
9. The CAM cell of claim 8 , wherein the gating transistor is an NMOS transistor, and the first and second pass transistors are NMOS transistors.
10. The CAM cell of claim 8 , wherein the logical combination comprises a logical NOR function.
11. A quaternary content addressable memory (CAM) cell for storing a data value having one of four possible states represented by first and second data bits, the CAM cell comprising:
first and second memory cells for storing the first and second data bits, respectively; and
a compare circuit to compare a comparand bit with the data value, the compare circuit comprising:
a single pull-down transistor coupled between the match line and ground potential, and having a gate coupled to a pull-down node; and
first and second gating transistors connected in series between the pull-down node and ground potential, the first gating transistor having a gate to receive the comparand bit, and the second gating transistor having a gate to receive a complemented comparand bit.
12. The CAM cell of claim 11 , wherein the single pull-down transistor is the only discharge path between the match line and ground potential.
13. The CAM cell of claim 11 , wherein the compare circuit further comprises:
a first pass transistor coupled between the second memory cell and the pull-down node, and having a gate to receive the complemented comparand bit; and
a second pass transistor coupled between the first memory cell and the pull-down node, and having a gate to receive the comparand bit.
14. The CAM cell of claim 13 , wherein the first and second gating transistors are NMOS transistors, and the first and second pass transistors are PMOS transistors.
15. A quaternary content addressable memory (CAM) cell for storing a data value having one of four possible states represented by first and second data bits, the CAM cell comprising:
first and second memory cells for storing the first and second data bits, respectively; and
a compare circuit to compare a comparand bit with the data value, the compare circuit comprising:
a single pull-down transistor coupled between the match line and ground potential, and having a gate coupled to a pull-down node;
a first pass transistor coupled between the first memory cell and the pull-down node, and having a gate to receive the comparand bit; and
a second pass transistor coupled between the second memory cell and the pull-down node, and having a gate to receive a complemented comparand bit.
16. The CAM cell of claim 15 , wherein the single pull-down transistor is the only discharge path between the match line and ground potential.
17. The CAM cell of claim 15 , wherein the compare circuit further comprises:
a gating transistor coupled between the pull-down node and ground potential, and having a gate responsive to a logical combination of the comparand bit and the complemented comparand bit.
18. The CAM cell of claim 17 , wherein the logical combination comprises a logical AND function.
19. The CAM cell of claim 17 , wherein the logical combination comprises a logical NOR function.
20. The CAM cell of claim 17 , wherein the gate of the gating transistor is coupled to a comparand signal gating line.
21. The CAM cell of claim 15 , further comprising:
a second compare circuit coupled to the first and second memory cells, and including a single discharge path between a second match line and ground potential, the single discharge path consisting essentially of a single discharge transistor.