IP Library Granted Patent US 8,711,532
Granted Patent B2
US 8,711,532 · App. 13/216,328 · Granted Apr 29, 2014

Integrated advance copper fuse combined with ESD/over-voltage/reverse polarity protection

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Quick Facts
Patent No.
US 8,711,532
App. No.
13/216,328
Granted
Apr 29, 2014
Kind
B2
Abstract

In one embodiment, an integrated circuit, and method of manufacturing thereof, is provided. The integrated circuit contains an over-voltage protection element and an over-current protection element. The integrated circuit operates to provide enhanced and efficient ESD functionality. The over-current element of the instant disclosure includes a diffusion protection layer to enhance the lifetime of the over-current element and improve functionality.

Claims (38)

1. An integrated circuit including a circuit-building substrate, the integrated circuit comprising:

a conductive structure, supported by the circuit-building substrate, including a metal track, and a diffusion-protector configured and arranged to lessen diffusion relative to the structure of the metal track, wherein the metal track is surrounded by and in contact with a first layer and a second layer of the diffusion-protector, wherein the first layer is deposited on the circuit-building substrate, the metal track covers the first layer, and the second layer covers the metal track;

an input terminal configured and arranged to present an input power-based signal to a first portion of the metal track;

an output terminal configured and arranged to pass an output power-based signal ensuing from the input power-based signal, to a second portion of the metal track; and

a voltage-surge circuit configured and arranged to pass the output power-based signal to a reference terminal in response to a voltage of the output power-based signal exceeding a voltage-threshold level associated with the circuit, whereby in response to a voltage surge exceeding the voltage-threshold level, the voltage-surge circuit is adapted to limit voltage levels supplied to electric circuitry connected at the output terminal by either shorting via the reference terminal or blocking with the metal track adapted to be sacrificed for over-current protection.

2. The integrated circuit of claim 1 , further including a circuit connected at the output terminal and cooperatively configured and arranged with the conductive structure and the voltage-surge circuit to be protected from over-voltage and over-current conditions, and wherein the diffusion-protector is further configured and arranged to mitigate oxidation of the metal track.

3. The integrated circuit of claim 1 , wherein the voltage-surge circuit provides a low-ohmic connection to the reference terminal.

4. The integrated circuit of claim 1 , wherein the metal track is copper.

5. The integrated circuit of claim 1 , wherein the metal track has a width between 50 and 200 micrometers.

6. The integrated circuit of claim 1 , wherein the metal track has a thickness of 1-2 micrometers.

7. The integrated circuit of claim 1 , wherein the metal track is adapted to operate a continuous working current that is not less than 2 Amps, and is adapted to be sacrificed at a current that is not greater than 5 Amps.

8. The integrated circuit of claim 1 , wherein the metal track is separated from the circuit-building substrate by a layer of isolating dielectric.

9. The integrated circuit of claim 1 , wherein the diffusion-protector includes TiN or TiWN located on opposite sides of the metal track.

10. The integrated circuit of claim 1 , wherein the voltage-surge circuit includes a p-n junction.

11. The integrated circuit of claim 1 , wherein the voltage-surge circuit includes a diode.

12. The integrated circuit of claim 1 , wherein the metal track is configured and arranged to connect the input terminal at one end of the metal track, and the output terminal at the opposite end of the metal track.

13. An integrated circuit including a circuit-building substrate, the integrated circuit comprising:

a conductive structure, supported by the circuit-building substrate, including a metal track, and a diffusion-protector configured and arranged to lessen diffusion relative to the structure of the metal track and to mitigate oxidation of the metal track, wherein the metal track is surrounded by and in contact with a first layer and a second layer of the diffusion-protector, wherein the first layer is deposited on the circuit-building substrate, the metal track covers the first layer, and the second layer covers the metal track;

an input terminal configured and arranged to present an input power-based signal to a first portion of the metal track;

an output terminal configured and arranged to pass an output power-based signal, ensuing from the input power-based signal, to a second portion of the metal track; and

a low-ohmic voltage-protection device configured and arranged to pass the output power-based signal to a reference terminal, in response to a voltage of the output power-based signal exceeding a voltage-threshold level associated with the circuit, wherein in response to a power-related signal at the input terminal presenting a voltage surge exceeding the voltage-threshold level and an over-current condition, the low-ohmic voltage-protection device is adapted to limit voltage levels supplied to electric circuitry connected at the output terminal by either shorting via the reference terminal or blocking while the metal track is heated in response to the over-current condition and then is sacrificed for over-current protection.

14. The integrated circuit of claim 13 , wherein the metal track is configured and arranged to withstand temperatures up to 200 degrees Centigrade.

15. The integrated circuit of claim 13 , wherein the metal track includes a first metal composition, and the diffusion-protector includes a second metal composition.

16. The integrated circuit of claim 13 , wherein the diffusion-protector is a thin layer of TiN or TiWN.

17. The integrated circuit of claim 13 , wherein the metal track is separated from the circuit-building substrate by a layer of isolating dielectric.

18. A method of manufacturing an integrated circuit including a circuit-building substrate, the integrated circuit comprising:

a conductive structure, supported by the circuit-building substrate, including a metal track, and a diffusion-protector configured and arranged to lessen diffusion relative to the structure of the metal track, wherein the metal track is surrounded by and in contact with a first layer and a second layer of the diffusion-protector, wherein the first layer is deposited on the circuit-building substrate, the metal track covers the first layer, and the second layer covers the metal track;

an input terminal configured and arranged to present an input power-based signal to a first portion of the metal track;

an output terminal configured and arranged to pass an output power-based signal ensuing from the input power-based signal, to a second portion of the metal track; and

a voltage-surge circuit configured and arranged to pass the output power-based signal to a reference terminal in response to a voltage of the output power-based signal exceeding a voltage-threshold level associated with the circuit, whereby in response to a voltage surge exceeding the voltage-threshold level, the voltage-surge circuit is adapted to limit voltage levels supplied to electric circuitry connected at the output terminal by either shorting via the reference terminal or blocking with the metal track adapted to be sacrificed for over-current protection,

the method comprising:

providing the substrate;

depositing the first layer of diffusion-protector on the substrate;

depositing the metal track on the first layer of diffusion-protector, the first layer of the diffusion-protector contacting the bottom side of the metal track;

depositing the second layer of diffusion-protector on the metal track, the second layer of diffusion-protector contacting the top side of the metal track;

providing an etch mask using lithography over the first layer of diffusion-protector, the metal track, and the second layer of diffusion-protector; and

etching the first layer of diffusion-protector, the metal track, and the second layer of diffusion-protector using lithography to expose the edges of the metal track and retain a portion of the first layer of diffusion protector on the bottom of the metal track, and portion of the second layer of diffusion protector the top of the metal track.

19. The method of claim 18 , wherein the first layer of diffusion-protector and the second layer of diffusion-protector include a barrier metal.

Assignments (12)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 13, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 048328/0964 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 8, 2016
From: NXP B.V.
To: NEXPERIA B.V.
Reel/Frame 039610/0734 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 038017/0058 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 24, 2011
From: PFENNIGSTORF, OLAF; SCHNITT, WOLFGANG
To: NXP B.V.
Reel/Frame 026797/0268 →