Field effect transistor and method for manufacturing semiconductor device
View Patent ↗A structure with which the zero current of a field effect transistor using a conductor-semiconductor junction can be reduced is provided. A floating electrode ( 102 ) including a conductor or a semiconductor and being enclosed by an insulator ( 104 ) is formed between a semiconductor layer ( 101 ) and a gate ( 105 ) so as to cross the semiconductor layer ( 101 ) and the floating electrode ( 102 ) is charged, whereby carriers are prevented from flowing from a source electrode ( 103 a ) or a drain electrode ( 103 b ). Accordingly, a sufficiently low carrier concentration can be kept in the semiconductor layer ( 101 ) and thus the zero current can be reduced.
1. A method for manufacturing a semiconductor device, comprising the steps of:
forming a semiconductor circuit comprising a field effect transistor, the field effect transistor comprising:
a semiconductor layer;
a first conductor electrode and a second conductor electrode in contact with a first surface of the semiconductor layer;
a gate over the first surface or a second surface of the semiconductor layer; and
a floating electrode between the semiconductor layer and the gate,
wherein the floating electrode comprises a conductor or a semiconductor and is enclosed by an insulator, and
wherein the floating electrode crosses the semiconductor layer;
charging the floating electrode with an electric charge; and
covering the semiconductor circuit with a light-blocking material after the step of charging the floating electrode,
wherein an amount of the electric charge in the floating electrode is not changed after charging.
2. The method for manufacturing a semiconductor device according to claim 1 , wherein the semiconductor layer comprises an oxide in which a proportion of indium and zinc to all metal elements is 25% or higher.
3. The method for manufacturing a semiconductor device according to claim 1 , wherein the semiconductor layer comprises an oxide having a bandgap greater than or equal to 3.0 eV and less than or equal to 4.5 eV.
4. The method for manufacturing a semiconductor device according to claim 1 ,
wherein the semiconductor layer comprises a first doped region and a second doped region,
wherein each of the first doped region and the second doped region includes a carrier at a higher concentration than the other region of the semiconductor layer,
wherein the first doped region is in contact with the first conductor electrode, and
wherein the second doped region is in contact with the second conductor electrode.
5. The method for manufacturing a semiconductor device according to claim 4 , wherein a carrier concentration of each of the first doped region and the second doped region is higher than or equal to 1×10 18 /cm 3 and lower than 1×10 21 /cm 3 .
6. The method for manufacturing a semiconductor device according to claim 1 , wherein in the step of charging, the amount of the electric charge in the floating electrode is determined so as to reduce variation in characteristics of the semiconductor circuit.
7. A method for manufacturing a semiconductor device, comprising the steps of:
forming a semiconductor circuit comprising a pad, and a field effect transistor, the field effect transistor comprising:
a semiconductor layer;
a first conductor electrode and a second conductor electrode in contact with a first surface of the semiconductor layer;
a gate over the first surface or a second surface of the semiconductor layer; and
a floating electrode between the semiconductor layer and the gate,
wherein the floating electrode comprises a conductor or a semiconductor and is enclosed by an insulator, and
wherein the floating electrode crosses the semiconductor layer; and
charging the floating electrode with an electric charge by applying voltage to the gate and one of the first conductor electrode and the second conductor electrode through the pad,
wherein an amount of the electric charge in the floating electrode is not changed after charging.
8. The method for manufacturing a semiconductor device according to claim 7 , wherein the semiconductor layer comprises an oxide in which a proportion of indium and zinc to all metal elements is 25% or higher.
9. The method for manufacturing a semiconductor device according to claim 7 , wherein the semiconductor layer comprises an oxide having a bandgap greater than or equal to 3.0 eV and less than or equal to 4.5 eV.
10. The method for manufacturing a semiconductor device according to claim 7 ,
wherein the semiconductor layer comprises a first doped region and a second doped region,
wherein each of the first doped region and the second doped region includes a carrier at a higher concentration than the other region of the semiconductor layer,
wherein the first doped region is in contact with the first conductor electrode, and
wherein the second doped region is in contact with the second conductor electrode.
11. The method for manufacturing a semiconductor device according to claim 10 , wherein a carrier concentration of each of the first doped region and the second doped region is higher than or equal to 1×10 18 /cm 3 and lower than 1×10 21 /cm 3 .
12. The method for manufacturing a semiconductor device according to claim 7 , wherein in the step of charging, the amount of the electric charge in the floating electrode is determined so as to reduce variation in characteristics of the semiconductor circuit.
13. A method for manufacturing a semiconductor device, comprising the steps of:
forming a semiconductor circuit comprising a field effect transistor, the field effect transistor comprising:
a semiconductor layer;
a first conductor electrode and a second conductor electrode in contact with a first surface of the semiconductor layer;
a gate over the first surface or a second surface of the semiconductor layer; and
a first region between the semiconductor layer and the gate,
wherein the first region crosses the semiconductor layer; charging the first region with an electric charge; and
covering the semiconductor circuit with a light-blocking material after the step of charging the first region,
wherein an amount of the electric charge in the first region is not changed after charging.
14. The method for manufacturing a semiconductor device according to claim 13 , wherein the semiconductor layer comprises an oxide in which a proportion of indium and zinc to all metal elements is 25% or higher.
15. The method for manufacturing a semiconductor device according to claim 13 , wherein the semiconductor layer comprises an oxide having a bandgap greater than or equal to 3.0 eV and less than or equal to 4.5 eV.
16. The method for manufacturing a semiconductor device according to claim 13 ,
wherein the semiconductor layer comprises a first doped region and a second doped region,
wherein each of the first doped region and the second doped region includes a carrier at a higher concentration than the other region of the semiconductor layer,
wherein the first doped region is in contact with the first conductor electrode, and
wherein the second doped region is in contact with the second conductor electrode.
17. The method for manufacturing a semiconductor device according to claim 16 , wherein a carrier concentration of each of the first doped region and the second doped region is higher than or equal to 1×10 18 /cm 3 and lower than 1×10 21 /cm 3.
18. The method for manufacturing a semiconductor device according to claim 13 , wherein in the step of charging, the amount of the electric charge in the first region is determined so as to reduce variation in characteristics of the semiconductor circuit.
19. The method for manufacturing a semiconductor device according to claim 13 , wherein the first region comprises a conductor or a semiconductor and is enclosed by an insulator.