Programmable resistance memory
View Patent ↗A memory includes a programmable resistance array with high ratio of dynamic range to drift coefficient phase change memory devices.
1. A method of operating a programmable resistance memory comprising:
providing a programmable resistance memory;
defining an operable resistance range for said memory, said resistance range extending from a minimum resistance to a maximum resistance;
specifying a first resistance for a first memory state;
specifying a second resistance for a second memory state, said second resistance exceeding said first resistance, said memory drifting from said first resistance to said second resistance in a first interval of time;
programming said memory to said first memory state at a first time;
reading said memory at a second time, said second time being later than said first time by less than said first interval of time;
specifying a third resistance for a third memory state, said third resistance exceeding said second resistance;
programming said memory to said second memory state at a third time, said second resistance drifting to said third resistance in a second interval of time; and
reading said memory at a fourth time, said fourth time being later than said third time by less than said second interval of time.
2. The method of claim 1 , wherein said programmable resistance memory comprises a phase-change material.
3. The method of claim 1 , wherein said first resistance is greater than said minimum resistance.
4. The method of claim 1 , wherein said second resistance is less than said maximum resistance.
5. A method of operating a programmable resistance memory comprising:
providing a programmable resistance memory;
defining an operable resistance range for said memory, said resistance range extending from a minimum resistance to a maximum resistance;
specifying a first resistance band for a first memory state, said first resistance band extending from a first lower resistance to a first upper resistance, said memory drifting from said first lower resistance to said first upper resistance in a first interval of time;
programming said memory to said first memory state at a first time;
reading said memory at a second time, said second time being later than said first time by less than said first interval of time;
specifying a second resistance band for a second memory state, said second resistance band extending from a second lower resistance to a second upper resistance, said memory drifting from said second lower resistance to said second upper resistance in a second interval of time;
programming said memory to said second memory state at a third time; and
reading said memory at a fourth time, said fourth time being later than said third time by less than said second interval of time.
6. The method of claim 5 , wherein said programmable resistance memory comprises a phase-change material.
7. The method of claim 5 , wherein said first lower resistance is greater than said minimum resistance.
8. The method of claim 5 , wherein said first upper resistance is less than said maximum resistance.
9. The method of claim 5 , wherein said second lower resistance is greater than said first upper resistance.
10. The method of claim 5 , wherein said second upper resistance is less than said maximum resistance.