Nonvolatile semiconductor memory device and method testing the same

1. A nonvolatile semiconductor memory device, comprising:

a memory cell array including a plurality of blocks arranged therein, each of the blocks including therein an aggregate of NAND cell units, each of the NAND cell units including therein memory strings, first and second select gate transistors connected to both ends of the memory string respectively, each of the memory string including therein a plurality of nonvolatile memory cells connected in series;

word lines each commonly connected to control gates of the memory cells arranged along a first direction;

first and second select gate lines each commonly connected to gates of the first or second select gate transistors arranged along the first direction;

bit lines each connected to a first end of the NAND cell unit;

a source line connected to a second end of the NAND cell unit;

a sense amplifier circuit configured to detect a potential of the bit lines to determine data stored in the memory cells;

a voltage control circuit configured to control voltages to be provided to the word lines, and the first and second select gate lines,

transfer transistors configured to switch a connection state between the voltage control circuit and the word lines, the first select gate line, and second select gate line; and

a control circuit configured to control the voltage control circuit, the transfer transistors and the sense amplifier circuit,

the control circuit being configured to, when performing a word line leak test to determine a leak state of the word lines,

apply, from the voltage control circuit to the word lines connected to the memory cell array written with test pattern data, voltages corresponding to the test pattern data,

thereafter switch the transfer transistors to a nonconductive state, thereby setting the word lines in a floating state,

after a lapse of a certain time from switching of the transfer transistors to a nonconductive state, activate the sense amplifier circuit to perform a read operation in the memory cell array, and

compare a result of the read operation with an expectation value corresponding to the test pattern data.

2. The nonvolatile semiconductor memory device according to claim 1 , wherein the sense amplifier circuit further includes a data buffer configured to hold data read by the word line leak test.

3. The nonvolatile semiconductor memory device according to claim 1 , wherein

among the memory cells in the memory string, a memory cell adjacent to the first or second select gate transistor is a dummy cell not used in for storing data.

4. The nonvolatile semiconductor memory device according to claim 3 , wherein

When the read operation is performed, the control circuit applies, to a dummy word line connected to the dummy cell, a read pass voltage that can turn on a memory cell regardless of data stored therein.

5. The nonvolatile semiconductor memory device according to claim 3 , wherein

When the read operation is performed, the control circuit applies, to a dummy word line connected to the dummy cell, the same voltage as a voltage applied to the first and second select gate lines.

6. The nonvolatile semiconductor memory device according to claim 1 , wherein

a piece of the test pattern data is either one of first data corresponding to the first threshold voltage distribution or second data corresponding to the second threshold voltage distribution that is higher than the first threshold voltage distribution, and

the control circuit applies a first voltage between first threshold voltage distribution and the second threshold voltage distribution to the word line connected to the memory cell to which the first data is written, and applies a second voltage that is larger than the upper limit of the second threshold voltage distribution to the word line connected to the memory cell to which the second data is written, and then switches the transfer transistors to a nonconductive state, thereby setting the word lines in a floating state.

7. The nonvolatile semiconductor memory device according to claim 6 , wherein

among the memory cells in the memory string, a memory cell adjacent to the first or second select gate transistor is a dummy cell not used in for storing data.

8. The nonvolatile semiconductor memory device according to claim 7 , wherein

When the read operation is performed, the control circuit applies, to a dummy word line connected to the dummy cell, a read pass voltage that can turn on a memory cell regardless of data stored therein.

9. The nonvolatile semiconductor memory device according to claim 7 , wherein

When the read operation is performed, the control circuit applies, to a dummy word line connected to the dummy cell, the same voltage as a voltage applied to the first and second select gate lines.

10. The nonvolatile semiconductor memory device according to claim 1 , wherein

the control circuit performs a first test operation after writing first data corresponding to a first threshold voltage distribution to even-numbered memory cells in the memory string, as the test pattern data, while writing second data corresponding to a second threshold voltage distribution to odd-numbered memory cells, as the test pattern data, the second threshold voltage distribution being higher than the first threshold voltage distribution,

and performs a second test operation after writing the first data to the odd-numbered memory cells in the memory string, as the test pattern data, while writing second data to the even-numbered memory cells, as the test pattern data.

11. The nonvolatile semiconductor memory device according to claim 10 , wherein

among the memory cells in the memory string, a memory cell adjacent to the first or second select gate transistor is a dummy cell not used in for storing data.

12. The nonvolatile semiconductor memory device according to claim 10 ,

wherein during the first test operation, the control circuit applies a first voltage between the first threshold voltage distribution and the second threshold voltage distribution to word lines connected to the even-numbered memory cells, while applies a second voltage larger than the upper limit of the second threshold voltage distribution to word lines connected to the odd-numbered memory cells, and

during the second test operation, the control circuit applies the first voltage to word lines connected to the odd-numbered memory cells, while applies the second voltage to word lines connected to the even-numbered memory cells.

13. The nonvolatile semiconductor memory device according to claim 1 , wherein

among the memory cells in the memory string, a memory cell adjacent to the first or second select gate transistor is a dummy cell not used in for storing data, and

a dummy word line connected to the dummy cell is provided with a voltage different from a voltage applied to a word line adjacent to the dummy word line.

14. The nonvolatile semiconductor memory device according to claim 1 , wherein

the control circuit switches a voltage applied to the transfer transistors from a first voltage to a second voltage, thereby maintaining the transfer transistor transferring a voltage smaller than the second voltage by a certain voltage in a conducting state.

15. A method of testing a nonvolatile semiconductor memory device, the device comprising: a memory cell array including a plurality of blocks arranged therein, each of the blocks including therein an aggregate of NAND cell units, each of the NAND cell units including therein memory strings, first and second select gate transistors connected to both ends of the memory string respectively, each of the memory string including therein a plurality of nonvolatile memory cells connected in series; word lines each commonly connected to control gates of the memory cells arranged along a first direction; first and second select gate lines each commonly connected to gates of the first or second select gate transistors arranged along the first direction; bit lines each connected to a first end of the NAND cell unit; a source line connected to a second end of the NAND cell unit; a sense amplifier circuit configured to detect a potential of the bit lines to determine data stored in the memory cells; a voltage control circuit configured to control voltages to be provided to the word lines, and the first and second select gate lines; and transfer transistors configured to switch a connection state between the voltage control circuit and the word lines, the first select gate line, and second select gate line,

the method comprising:

writing test pattern data to the memory cell array;

after applying a voltage corresponding to the test pattern data to word lines connected to the memory cell array written with the test pattern data, switching the transfer transistors to a nonconductive state, thereby setting the word lines in a floating state;

after a lapse of a certain time from switching of the transfer transistors to a nonconductive state, activating the sense amplifier circuit to perform a read operation in the memory cell array; and

comparing a result of the read operation with an expectation value corresponding to the test pattern data.

16. The method of testing according to claim 15 , further comprising:

performing a first test operation by executing a voltage application operation, and the read operation after writing first data corresponding to a first threshold voltage distribution to even-numbered memory cells in the memory string, as the test pattern data, while writing second data corresponding to a second threshold voltage distribution to odd-numbered memory cells, as the test pattern data, the second threshold voltage distribution being higher than the first threshold voltage distribution; and

performing a second test operation by executing a voltage application operation, and the read operation after writing the first data to the odd-numbered memory cells in the memory string, as the test pattern data, while writing second data to the even-numbered memory cells.

17. The method of testing according to claim 16 , wherein

during the first test operation, a first voltage between the first threshold voltage distribution and the second threshold voltage distribution is applied to word lines connected to the even-numbered memory cells, while a second voltage larger than the upper limit of the second threshold voltage distribution is applied to word lines connected to the odd-numbered memory cells, and

during the second test operation, the first voltage is applied to word lines connected to the odd-numbered memory cells, while the second voltage is applied to word lines connected to the even-numbered memory cells.

18. The method of testing according to claim 15 , wherein

among the memory cells in the memory string, a memory cell adjacent to the first or second select gate transistor is a dummy cell not used in for storing data, and

a dummy word line connected to the dummy cell is provided with a voltage different from a voltage applied to a word line adjacent to the dummy word line.

19. The method of testing according to claim 15 , wherein

a voltage applied to the transfer transistors is switched from a first voltage to a second voltage, thereby maintaining the transfer transistor transferring a voltage smaller than the second voltage by a certain voltage in a conducting state.

20. The method of testing according to claim 15 , wherein

a piece of the test pattern data is either one of first data corresponding to the first threshold voltage distribution or second data corresponding to the second threshold voltage distribution that is higher than the first threshold voltage distribution, and

a first voltage between first threshold voltage distribution and the second threshold voltage distribution is applied to the word line connected to the memory cell to which the first data is written, and a second voltage that is larger than the upper limit of the second threshold voltage distribution is applied to the word line connected to the memory cell to which the second data is written, and then the transfer transistors is switched to a nonconductive state, thereby setting the word lines in a floating state.