IP Library Granted Patent US 8,497,146
Granted Patent B2
US 8,497,146 · App. 13/218,289 · Granted Jul 30, 2013

Vertical solid-state transducers having backside terminals and associated systems and methods

Inventors: Vladimir Odnoblyudov (Eagle, ID); Martin F. Schubert (Boise, ID)
Assignee: Micron Technology, Inc.
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Quick Facts
Patent No.
US 8,497,146
App. No.
13/218,289
Granted
Jul 30, 2013
Kind
B2
Abstract

Vertical solid-state transducers (“SSTs”) having backside contacts are disclosed herein. An SST in accordance with a particular embodiment can include a transducer structure having a first semiconductor material at a first side of the SST, a second semiconductor material at a second side of the SST opposite the first side, and an active region between the first and second semiconductor materials. The SST can further include first and second contacts electrically coupled to the first and second semiconductor materials, respectively. A portion of the first contact can be covered by a dielectric material, and a portion can remain exposed through the dielectric material. A conductive carrier substrate can be disposed on the dielectric material. An isolating via can extend through the conductive carrier substrate to the dielectric material and surround the exposed portion of the first contact to define first and second terminals electrically accessible from the first side.

Claims (45)

1. A method of forming solid-state transducers (SSTs) having a first side and second side facing away from the first side, the method comprising:

forming a transducer structure having an active region positioned between a first semiconductor material and a second semiconductor material, wherein the first semiconductor material is at the first side of the SST and the second semiconductor material is at the second side of the SST, wherein forming the transducer structure comprises forming the transducer structure on a growth substrate, the second semiconductor material being proximate to the growth substrate;

forming a first contact electrically coupled to the first semiconductor material;

forming a buried second contact electrically coupled to the second semiconductor material;

disposing a conductive carrier substrate on the first side of the SST, and electrically coupling the first and second contacts to the conductive carrier substrate;

forming a first terminal from a first portion of the conductive carrier substrate, the first terminal being electrically coupled to the first contact; and

forming a second terminal from a second portion of the conductive carrier substrate, the second terminal being electrically coupled to the second contact and electrically isolated from the first terminal, the first and second terminals both being accessible from the first side of the SST;

forming a plurality of trenches extending from the first side of the SST at least partially into the growth substrate;

forming separators in the trenches that demarcate individual SSTs; and

removing the growth substrate from the second semiconductor material such that at least a portion of each separator extends beyond the second semiconductor material to form a plurality of protrusions.

2. The method of claim 1 , further comprising:

forming a dielectric material on the first semiconductor material and the first contact before forming the conductive carrier substrate, wherein the first contact includes an exposed portion not covered by the dielectric material;

forming a plurality of buried contact elements extending from the first side of the SST to at least the second semiconductor material;

forming conductive lines on the dielectric material interconnecting the buried contact elements, wherein the conductive lines and the buried contact elements define the second contact;

forming a dielectric portion on the second contact, wherein the second contact includes an exposed portion not covered by the dielectric portion;

forming a metal material on the dielectric portion, the dielectric material, and the exposed portions of the first and second contacts;

wherein disposing the conductive carrier substrate comprises plating a copper substrate on the metal material; and

wherein forming the first terminal comprises forming an isolating via around the exposed portion of the first contact, the isolating via extending through the conductive carrier substrate to at least the dielectric material.

3. The method of claim 1 wherein forming the second contact comprises:

forming a plurality of trenches extending from the first side of the SST to at least the second semiconductor material;

coating sidewalls of the trenches with a dielectric material;

forming a contact material in the trenches to define a plurality of buried contact elements, wherein the contact material is electrically coupled to the second semiconductor material;

forming a dielectric material on the first contact and the first semiconductor material, wherein the buried contact elements and a portion of the first contact are not covered by the dielectric material; and

forming conductive lines on the dielectric material interconnecting the buried contact elements.

4. The method of claim 1 wherein forming the conductive carrier substrate comprises:

forming a barrier material on the first side of the SST, wherein the barrier material is electrically coupled to the first and second contacts;

forming a seed material on the barrier material;

forming the isolating via through the barrier and seed materials, the isolating via being configured to decouple the first contact from the second contact; and

plating a copper substrate on the seed material.

5. The method of claim 1 wherein:

forming the first terminal comprises forming a first isolating via extending through the conductive carrier substrate to an underlying dielectric material, wherein the first isolating via surrounds portions of the first contact not covered by the dielectric material; and

forming the second terminal comprises forming a second isolating via extending through the conductive carrier substrate to the dielectric material, wherein the second isolating via surrounds portions of the second contact not covered by the dielectric material.

6. The method of claim 1 wherein:

forming the separators comprises forming a dielectric isolator, a barrier material, and a seed material in the trenches; and

forming the conductive carrier substrate comprises plating a metal substrate on the seed material, the metal substrate extending partially into the trenches.

7. The method of claim 1 , further comprising forming converter elements on the second side of the SST, wherein individual converter elements are separated by the protrusions.

8. The method of claim 7 wherein forming the converter elements comprises:

forming a first converter element on a first SST, wherein the first converter element is configured to emit a first color of light; and

forming a second converter element on a second SST, wherein the second converter element is configured to emit a second color of light different from the first color, and wherein the second SST and the second converter element are separated from the first SST and the first converter element by an adjoining separator.

9. The method of claim 1 , further comprising forming cover elements on the second side of the SST, wherein individual cover elements are separated by the protrusions.

10. The method of claim 1 , further comprising dicing along dicing lanes aligned with the protrusions.

11. The method of claim 1 , further comprising:

testing the individual SSTs; and

dicing the SSTs along dicing lanes after testing the SSTs, wherein the dicing lanes are aligned with the protrusions.

12. The method of claim 1 wherein forming the transducer structure comprises forming a transducer structure configured to emit electromagnetic radiation in at least one of the ultraviolet spectrum, the visible spectrum, and the infrared spectrum.

Assignments (8)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2011
From: ODNOBLYUDOV, VLADIMIR; SCHUBERT, MARTIN F.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 026810/0465 →
Continuity (1)
Related Publication 20130052759A1 · Feb 28, 2013