Methods of manufacturing power semiconductor devices with shield and gate contacts

1. A method of manufacturing a semiconductor device comprising:

forming an epitaxial layer over a substrate; forming a dielectric layer over the epitaxial layer and patterning the dielectric layer; etching the patterned dielectric layer to form an active trench in the portions of the dielectric layer that have been patterned to not have dielectric layer; forming a first oxide layer across a top surface of the substrate including the active trench; forming a first conductive layer on top of the first oxide layer; etching the first conductive layer away inside the active trench forming a second oxide layer over the first conductive layer; forming a second conductive layer on top of the second oxide layer, wherein the second conductive layer does not extend completely over the first conductive layer in a first edge region outside of the active trench; forming a third oxide layer over the second conductive layer; etching a first opening through the third oxide layer to expose the second conductive layer outside of the active trench; etching a second opening through the second oxide layer outside of the active trench to expose the first conductive layer but not the second conductive layer; the first opening and the second opening located in the first edge region and filling the first opening and the second opening with a conductive material.

2. The method of claim 1 further comprising forming plurality of active trenches in the longitudinal direction and forming a perimeter trench with a plurality of extensions in the longitudinal direction that are staggered with respect to the active trenches so that there is an offset between the plurality of extensions of the perimeter trench and the active trenches.

3. The method of claim 1 further comprising forming plurality of active trenches in the longitudinal direction and forming a perimeter trench with a plurality of extensions in the longitudinal direction that are staggered with respect to the active trenches so that there is no offset between the plurality of extensions of the perimeter trench and the active trenches.

4. The method of claim 1 further comprising forming a third conductive layer over the third oxide layer and contacting the conductive material in the first opening and the second opening to electrically connect the first conductive layer and the second conductive layer.

5. The method of claim 1 further comprising electrically connecting the first opening to a first metal contact and the second opening to a second metal contact.

6. The method of claim 1 wherein the step of depositing a dielectric layer further comprises depositing a layer of silicon dioxide.

7. The method of claim 1 wherein the first conductive layer, the second conductive layer are polysilicon.

8. The method of claim 1 wherein

the first conductive layer is directly formed over the first oxide layer;

the second oxide layer is directly formed over the first conductive layer;

the second conductive layer is directly formed over the second oxide layer; and

the third oxide layer is directly formed over the second conductive layer.

9. The method of claim 1 wherein the first conductive layer and the second conductive layer are formed with substantially the same thickness.

10. A method of manufacturing a semiconductor device comprising:

forming an epitaxial layer over a substrate; forming a dielectric layer over the epitaxial layer and patterning the dielectric layer; etching the patterned dielectric layer to form an active trench in the portions of the dielectric layer that have been patterned to not have dielectric layer; forming a first oxide layer across a top surface of the substrate including the active trench; forming a first conductive layer on top of the first oxide layer; etching the first conductive layer away inside the active trench forming a second oxide layer over the first conductive layer; forming a second conductive layer on top of the second oxide layer, wherein the second conductive layer does not extend completely over the first conductive layer in a first edge region outside of the active trench;

forming a third oxide layer over the second conductive layer;

etching a first opening through the third oxide layer to expose the second conductive layer in the first edge region outside of the active trench; etching a second opening through the second oxide layer outside of the active trench in the first edge region to expose the first conductive layer but not the second conductive layer; and filling the first opening and the second opening with a conductive material.

11. A method of manufacturing a semiconductor device comprising:

forming an epitaxial layer over a substrate; forming a dielectric layer over the epitaxial layer and patterning the dielectric layer; etching the patterned dielectric layer to form an active trench in the portions of the dielectric layer that have been patterned to not have dielectric layer; forming a first oxide layer across a top surface of the substrate including the active trench; forming a first conductive layer on top of the first oxide layer; etching the first conductive layer away inside the active trench forming a second oxide layer over the first conductive layer; forming a second conductive layer on top of the second oxide layer, wherein the second conductive layer does not extend completely over the first conductive layer in a first region outside of the active trench; forming a third oxide layer over the second conductive layer; etching a first opening through the third oxide layer to expose the second conductive layer in the first region outside of the active trench; etching a second opening through the second oxide layer outside of the active trench to expose the first conductive layer but not the second conductive layer, the first opening and the second opening on a same side of the active trench; and filling the first opening and the second opening with a conductive material.