Memory sensing using temperature compensated initial currents

1. A method for sensing a memory cell, comprising:

applying a number of temperature compensated initial currents to sense circuitry, wherein applying the number of temperature compensated initial currents includes:

using temperature compensation circuitry to determine a multiple; and

mirroring a number of initial currents by the multiple;

generating, by the sense circuitry, a number of read reference currents and program reference currents based on a plurality of the temperature compensated initial currents, wherein the number of read reference currents and program reference currents is greater than the number of temperature compensated initial currents; and

sensing a memory cell using one of the number of read reference currents and program reference currents.

2. The method of claim 1 , wherein:

the number of temperature compensated initial currents is three; and

the number of read reference currents and program reference currents is five.

3. The method of claim 1 , wherein applying the number of temperature compensated initial currents to sense circuitry includes applying the number of temperature compensated initial currents to a number of sense amplifiers.

4. A method for sensing a memory cell, comprising:

applying a number of temperature compensated initial currents to sense circuitry, wherein:

applying the number of temperature compensated initial currents includes adjusting a width ratio of a pair of NMOS transistor widths;

adjusting the width ratio of the pair of NMOS transistor widths includes using logic to adjust an output of a series of transistors coupled to the pair of NMOS transistors; and

sensing a memory cell using one of a number of read reference currents and a number of program reference currents, wherein:

the number of read reference currents and the number of program reference currents are generated by the sense circuitry;

the number of read reference currents and program reference currents is greater than the number of temperature compensated initial currents; and

the number of read reference currents and the number of program reference currents are based on a plurality of the temperature compensated initial currents.

5. The method of claim 4 , wherein generating the number of program reference currents includes generating the number of program reference currents such that a value of each program reference current is located between values of two read reference currents.

6. The method of claim 4 , wherein applying a number of temperature compensated initial currents includes applying a number of temperature compensated currents having unique temperature coefficients.

7. The method of claim 4 , wherein applying a number of temperature compensated initial currents includes:

using temperature compensation circuitry to determine a multiple; and

mirroring a number of initial currents by the multiple.

8. The method of claim 7 , wherein using temperature compensation circuitry to determine the multiple includes using a temperature sensor.

9. A memory device, comprising:

current providing circuitry configured to provide a number of initial currents, wherein:

the current providing circuitry includes temperature compensation circuitry configured to adjust the number of initial currents in response to a change in temperature; and

the temperature compensation circuitry includes:

a first group of sets of fuses, wherein each set of fuses in the first group represent a magnitude of a corresponding initial current at a particular temperature; and

a second group of sets of fuses, wherein each set of fuses in the second group correspond to a difference in magnitude of a corresponding initial current between a high pre-defined temperature and a low pre-defined temperature;

sense circuitry coupled to the current providing circuitry, wherein:

the initial currents are applied to the sense circuitry; and

the sense circuitry is configured to generate a number of read reference currents and program reference currents, wherein:

the number of read reference currents and program reference currents is greater than the number of initial currents; and

the read reference currents and the program reference currents are based on a plurality of the initial currents; and

at least one memory cell coupled to the sense circuitry.

10. The device of claim 9 , wherein the at least one memory cell is a phase change random access memory (PCRAM) cell.

11. The device of claim 10 , wherein the PCRAM cell includes a Germanium-Antimony-Tellurium (GST) material.

12. The device of claim 9 , wherein the temperature compensation circuitry includes a number of mirroring transistors, wherein each mirror transistor is configured to mirror the number of initial currents by a different multiple.

13. A memory device, comprising:

current providing circuitry configured to provide a number of temperature compensated initial currents; and

sense circuitry coupled to the current providing circuitry, wherein:

the sense circuitry is configured to generate a number of read reference currents and a number of program reference currents;

the number of read reference currents and program reference currents is greater than the number of initial currents;

the read reference currents and program reference currents are based on a plurality of the initial currents; and

the sense circuitry includes:

a first set of transistors, wherein each transistor in the first set of transistors is coupled to one of the temperature compensated initial currents;

a second set of transistors, wherein each transistor in the second set of transistors is coupled to one of the transistors in the first set of transistors; and

logic circuitry configured to selectively turn on one or more of the transistors in the second set of transistors.

14. The device of claim 13 , wherein:

the device includes at least one resistance variable memory cell coupled to the sense circuitry, wherein the resistance variable memory cell is capable of storing a number of data states; and

one or more of the data states are favored.

15. The device of claim 13 , wherein:

each transistor in the first set of transistors is an NMOS transistor; and

each transistor in the second set of transistors is an NMOS transistor.

16. The device of claim 13 , wherein:

each transistor in the first set of transistors is a PMOS transistor; and

each transistor in the second set of transistors in a PMOS transistor.

17. The device of claim 13 , wherein:

a first temperature compensated initial current is coupled to a first transistor in the first set of transistors;

the first transistor in the first set of transistors is coupled to a first transistor in the second set of transistors;

a second temperature compensated initial current is coupled to a second transistor and a third transistor in the first set of transistors;

the second transistor in the first set of transistors is coupled to a second transistor in the second set of transistors;

the third transistor in the first set of transistors is coupled to a third transistor in the second set of transistors;

a third temperature compensated initial current is coupled to a fourth transistor and a fifth transistor in the first set of transistors;

the fourth transistor in the first set of transistors is coupled to a fourth transistor in the second set of transistors; and

the fifth transistor in the first set of transistors is coupled to a fifth transistor in the second set of transistors.

18. The device of claim 13 , wherein the number of temperature compensated initial currents are DC bandgap-generated currents, wherein the DC bandgap generated circuits have been mirrored by a multiple.

19. A memory device, comprising:

current providing circuitry configured to provide a number of initial currents, wherein:

the current providing circuitry includes temperature compensation circuitry configured to adjust the number of initial currents in response to a change in temperature; and

the temperature compensation circuitry includes a number of mirroring transistors, wherein each mirror transistor is configured to mirror the number of initial currents by a different multiple;

sense circuitry coupled to the current providing circuitry, wherein:

the initial currents are applied to the sense circuitry; and

the sense circuitry is configured to generate a number of read reference currents and program reference currents, wherein:

the number of read reference currents and program reference currents is greater than the number of initial currents; and

the read reference currents and the program reference currents are based on a plurality of the initial currents; and

at least one memory cell coupled to the sense circuitry.

20. A memory device, comprising:

current providing circuitry configured to provide a number of temperature compensated initial currents, wherein the number of temperature compensated initial currents are DC bandgap-generated currents, wherein the DC bandgap generated circuits have been mirrored by a multiple; and

sense circuitry coupled to the current providing circuitry, wherein:

the sense circuitry is configured to generate a number of read reference currents and a number of program reference currents;

the number of read reference currents and program reference currents is greater than the number of initial currents; and

the read reference currents and program reference currents are based on a plurality of the initial currents.