Semiconductor device
View Patent ↗In a semiconductor device of the invention, a semiconductor pillar configuring a vertical MOS transistor has an upper pillar having a first width and a lower pillar having a second width. A side surface of the upper pillar is covered with a second insulation film and a third insulation film and the lower pillar is covered with a first insulation film, which is a gate insulation film, from a side surface thereof to the second insulation film. A gate electrode is insulated from an upper conductive layer by the second and third insulation films.
1. A semiconductor device comprising a vertical MOS transistor having upper and lower conductive layers at upper and lower parts thereof in a normal direction of a semiconductor substrate, the vertical MOS transistor comprising:
a first semiconductor pillar comprising a first upper pillar having a first width and a first lower pillar having a second width larger than the first width and an upper surface around the first upper pillar on a main surface of the semiconductor substrate;
a first insulation film that is provided on a side surface to at least a part of the upper surface of the first lower pillar;
a second insulation film that is provided on a side surface of at least a part of the first upper pillar, and
a third insulation film provided on the second insulation film and upwardly extended beyond an upper surface of the first semiconductor pillar,
wherein the side surface of the first semiconductor pillar is continuously covered with the first and second insulation films.
2. The semiconductor device according to claim 1 , wherein the first insulation film is extended to a part of the side surface of the first upper pillar not covered with the second insulation film.
3. The semiconductor device according to claim 1 , wherein the second insulation film covers a whole side surface of the first upper pillar and provided on a part of the upper surface of the first lower pillar.
4. The semiconductor device according to claim 1 , wherein the second insulation film and the third insulation film are made of different materials, respectively.
5. The semiconductor device according to claim 4 , wherein the second insulation film is a silicon oxide film and the third insulation film is a silicon nitride film or silicon oxynitride film.
6. The semiconductor device according to claim 1 , wherein the second insulation film is thicker than the first insulation film.
7. The semiconductor device according to claim 5 , wherein the third insulation film is separated from the first insulation film to form a space therebetween and the first semiconductor pillar further comprises a first conductive film that covers a whole surface of the first insulation film and at least a part of the third insulation film and is provided to fill the space.
8. The semiconductor device according to claim 7 , wherein the upper conductive layer is provided on an upper surface of the first semiconductor pillar, and
wherein the upper conductive layer and the first conductive film are insulated by at least the second and third insulation films.
9. The semiconductor device according to claim 8 , wherein the upper conductive layer comprises an epitaxially grown semiconductor layer containing impurities having an opposite conduction type to impurities in the semiconductor substrate.
10. The semiconductor device according to claim 7 , a part of the third insulation film contacts the first upper pillar via the second insulation film and a bottom part of the third insulation film contacts the first lower pillar via the first insulation film and the first conductive film.
11. The semiconductor device according to claim 7 , wherein the first insulation film and the first conductive film are a gate insulation film and a gate electrode of the vertical MOS transistor, respectively.
12. The semiconductor device according to claim 11 , further comprising a dummy pillar that is adjacent to the first semiconductor pillar configuring the vertical MOS transistor;
wherein the dummy pillar comprises:
a second semiconductor pillar on a main surface of the semiconductor substrate,
the first insulation film covering on at least a part of a side surface of the second semiconductor pillar, and
a second conductive film insulated from the second semiconductor pillar; and
wherein the second conductive film contacts with the first conductive film that is the gate electrode of the vertical MOS transistor.
13. The semiconductor device according to claim 12 , wherein the second semiconductor pillar comprises a second upper pillar having a third width and a second lower pillar having a fourth width larger than the third width and an upper surface around the upper pillar;
wherein the first insulation film is provided on a side surface to at least a part of the upper surface of the second lower pillar;
wherein the second insulation film is provided on a side surface of at least a part of the second upper pillar;
wherein the third insulation film is provided on the second insulation film and upwardly extended beyond an upper surface of the second semiconductor pillar;
wherein the dummy pillar comprises fourth and fifth insulation films that have the same planar shapes as that of the second upper pillar on an upper surface of the second upper pillar;
wherein the side surface of the second semiconductor pillar is continuously covered with the first and second insulation films; and
wherein the third insulation film is separated from the first insulation film on the second lower pillar to form a space therebetween and the second conductive film covers a whole surface of the first insulation film on the second lower pillar and at least a part of the third insulation film and is provided to fill the space.
14. The semiconductor device according to claim 13 , wherein the second semiconductor pillar has a same height with the first semiconductor pillar and the second lower pillar has a same height with the first lower pillar.
15. The semiconductor device according to claim 13 , wherein the third width of the second upper pillar is wider than the first width of the first upper pillar and the third width of the second lower pillar is wider than the second width of the first lower pillar.
16. The semiconductor device according to claim 12 , further comprising a contact connected to the second conductive film provided to the dummy pillar.
17. The semiconductor device according to claim 1 , wherein the vertical MOS transistor is provided in an active area that is surrounded by a shallow trench isolation formed in the semiconductor substrate.
18. The semiconductor device according to claim 17 , wherein an upper surface of an insulation film of the shallow trench isolation is position at an approximately same plane with the upper surface of the first semiconductor pillar.
19. The semiconductor device according to claim 1 , further comprising at least three contacts electrically connected to the lower conductive layer, the upper conductive layer of the vertical MOS transistor and the first conductive layer, respectively.
20. The semiconductor device according to claim 1 , further comprising a capacitor that is electrically connected to the upper conductive layer of the vertical MOS transistor.