Non-planar semiconductor structure and fabrication method thereof
View Patent ↗A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. A non-planar semiconductor process is also provided for forming the semiconductor structure.
1. A non-planar semiconductor structure, comprising:
a substrate;
at least two fin-shaped structures located on the substrate;
at least an isolation structure located between the fin-shaped structures, the isolation structure having a nitrogen-containing layer; and
a plurality of epitaxial layers respectively covering a part of the fin-shaped structures and located on the nitrogen-containing layer.
2. The non-planar semiconductor structure according to claim 1 , wherein the substrate comprises a silicon substrate or a silicon-on-insulator substrate.
3. The non-planar semiconductor structure according to claim 1 , further comprising a gate structure covering the fin-shaped structures between the epitaxial layers.
4. The non-planar semiconductor structure according to claim 3 , wherein the gate structure further comprises:
a gate dielectric layer covering the fin-shaped structures;
a gate electrode covering the gate dielectric layer;
a cap layer covering the gate electrode; and
a spacer located beside the gate dielectric layer, the gate electrode and the cap layer.
5. The non-planar semiconductor structure according to claim 1 , wherein the nitride layer comprises a silicon nitride layer or a silicon oxynitride layer.
6. The non-planar semiconductor structure according to claim 1 , wherein the nitrogen-containing layer is also located between the fin-shaped structures and the epitaxial layers.
7. A semiconductor process, comprising:
providing a substrate;
forming at least two fin-shaped structures on the substrate;
forming an oxide layer between the fin-shaped structures;
forming a nitrogen-containing layer in the oxide layer; and
performing an epitaxial process to form a plurality of epitaxial layers covering the fin-shaped structures.
8. The semiconductor process according to claim 7 , wherein the substrate comprises a silicon substrate or a silicon-on-insulator substrate.
9. The semiconductor process according to claim 8 , wherein the steps of forming the fin-shaped structures on the silicon substrate comprise:
forming a mask layer on the silicon substrate;
patterning the mask layer and etching the silicon substrate to form the fin-shaped structures by using the patterned mask layer.
10. The semiconductor process according to claim 9 , wherein the mask layer comprises a pad oxide layer and a nitride layer.
11. The semiconductor process according to claim 8 , wherein the silicon-on-insulator substrate comprises:
a substrate;
a bottom oxide layer located on the substrate; and
a silicon layer located on the bottom oxide layer.
12. The semiconductor process according to claim 11 , wherein the steps of forming the fin-shaped structures on the silicon-on-insulator substrate and forming the oxide layer between the fin-shaped structures comprise:
patterning the silicon layer to form the fin-shaped structures and expose a part of the bottom oxide layer between the fin-shaped structures.
13. The semiconductor process according to claim 7 , wherein forming the nitrogen-containing layer comprises:
performing a nitridation process to nitridate the surface of the oxide layer to form the nitrogen-containing layer in the oxide layer.
14. The semiconductor process according to claim 13 , wherein the nitridation process comprises a decoupled plasma nitridation process, an ammonia-containing annealing process, a remote plasma nitridation process, or a thermal nitridation process.
15. The semiconductor process according to claim 13 , further comprising:
performing a post-nitridation annealing process after performing the nitridation process.
16. The semiconductor process according to claim 15 , wherein the post-nitridation annealing process comprises an ammonia-containing annealing process.
17. The semiconductor process according to claim 7 , wherein the nitrogen-containing layer is formed between the oxide layer and the epitaxial layers and between the epitaxial layers and the fin-shaped structures.
18. The semiconductor process according to claim 7 , further comprising:
after forming the oxide layer, forming a gate structure on a part of the oxide layer and a part of the fin-shaped structures, wherein the epitaxial layers are located beside the gate structure.
19. The semiconductor process according to claim 7 , further comprising:
after forming the nitride layer, forming a gate structure on a part of the oxide layer and a part of the fin-shaped structures, wherein the epitaxial layers located beside the gate structure.