Integrated circuit device
A semiconductor device along with circuits including same and methods of operating same are disclosed. In one particular embodiment, the device may comprise a memory cell including a transistor. The transistor may comprise a gate, an electrically floating body region, and a source region and a drain region adjacent the body region. Data stored in memory cells of the device may be refreshed during hold operations.
1. An integrated circuit device comprising:
a memory cell comprising a transistor, the transistor comprising a gate, a body region configured to be electrically floating, and a source region and a drain region adjacent the body region; and
hold circuitry coupled to the memory cell, the hold circuitry to apply a set of hold signals to the transistor except during read operations and write operations, wherein the set of hold signals hold a data state of the transistor by refreshing the data state, wherein the data state comprises a logic high data state and a logic low data state, wherein the set of hold signals cause bipolar current to flow in the body region when the body region is in the logic high data state.
2. The integrated circuit device of claim 1 , wherein the transistor retains the data state as long as the hold signals are applied.
3. The integrated circuit device of claim 1 , wherein the source region, the body region, and the drain region function as the emitter, the base, and the collector of a bipolar transistor, respectively.
4. The integrated circuit device of claim 1 , wherein
the set of hold signals fail to cause bipolar current to flow in the body region when the body region is in the logic low data state.
5. The integrated circuit device of claim 1 , wherein the set of hold signals comprises a first potential applied to the gate, and a second potential applied between the source region and the drain region.
6. The integrated circuit device of claim 5 , wherein the first potential comprises a voltage of approximately −0.7 volts.
7. The integrated circuit device of claim 5 , wherein the second potential comprises a voltage approximately in a range of 1.5 volts to 3.2 volts.
8. The integrated circuit device of claim 5 , wherein the second potential comprises a voltage of approximately 2.3 volts.
9. The integrated circuit device of claim 5 , wherein:
when the body region of the transistor is in the logic high data state, the second potential is greater than a threshold above which bipolar current is generated in the body region and the second potential difference causes bipolar current to flow in the body region resulting from an increase of majority carriers in the body region due to impact ionization; and
when the body region of the transistor is in the logic low data state, the second potential is less than the threshold, wherein the flow of bipolar current is absent in the body region.
10. The integrated circuit device of claim 1 , wherein the gate is disposed over a first portion of the body region.
11. The integrated circuit device of claim 10 , wherein the source region adjoins a second portion of the body region that is adjacent the first portion and separates the source region from the first portion.
12. The integrated circuit device of claim 11 , wherein the drain region adjoins a third portion of the body region that is adjacent the first portion and separates the drain region from the first portion.
13. The integrated circuit device of claim 1 , wherein one or more of the source region and the drain region comprise a doped region shaped so that a boundary of the doped region is separated from a portion of the body region underlying the gate.
14. The integrated circuit device of claim 1 , wherein the body region comprises a first type of semiconductor material and the source region and drain region comprise a second type of semiconductor material.
15. The integrated circuit device of claim 14 , wherein the source region comprises a lightly doped region.
16. The integrated circuit device of claim 14 , wherein the source region comprises a highly doped region.
17. The integrated circuit device of claim 14 , wherein the source region comprises a lightly doped region and a highly doped region.
18. The integrated circuit device of claim 14 , wherein the drain region comprises a lightly doped region.
19. The integrated circuit device of claim 14 , wherein the drain region comprises a highly doped region.
20. The integrated circuit device of claim 14 , wherein the drain region comprises a lightly doped region and a highly doped region.