System and method for manufacturing three dimensional integrated circuits

1. A method for manufacturing three-dimensional integrated circuits, comprising:

providing an imaging writer system, wherein the imaging writer system includes a plurality of spatial light modulator (SLM) imaging units arranged in one or more parallel arrays;

receiving mask data to be written to one or more layers of the three-dimensional integrated circuit;

processing the mask data to form a plurality of partitioned mask data patterns corresponding to the one or more layers of the three-dimensional integrated circuit, wherein processing the mask data comprises arranging a placement of one or more layout blocks in the one or more layers of the three-dimensional integrated circuit, and identifying through silicon vias for routing communication signals between the one or more layout blocks in the one or more layers of the three-dimensional integrated circuit;

assigning one or more SLM imaging units to handle each of the partitioned mask data pattern; and

controlling the plurality of SLM imaging units to write the plurality of partitioned mask data patterns to the one or more layers of the three-dimensional integrated circuits in parallel.

2. The method of claim 1 , wherein assigning one or more SLM imaging units comprises:

performing scaling corrections on the plurality of partitioned mask data patterns in accordance with the plurality of SLM imaging units, wherein each of the partitioned mask data pattern has a corresponding scaling correction.

3. The method of claim 1 , wherein assigning one or more SLM imaging units further comprises:

performing alignment corrections on the plurality of partitioned mask data patterns in accordance with the plurality of SLM imaging units, wherein each of the partitioned mask data pattern has a corresponding alignment correction; and

performing subsequent alignment corrections in multiple exposures of the partitioned mask data pattern.

4. The method of claim 1 , wherein assigning one or more SLM imaging units further comprises:

performing inter-ocular displacement corrections on the plurality of partitioned mask data patterns in accordance with the plurality of SLM imaging units, wherein each of the partitioned mask data pattern has a corresponding inter-ocular displacement correction; wherein performing inter-ocular displacement correction comprises measuring the inter-ocular displacements among the plurality of SLM imaging units, calibrating the plurality of partitioned mask data patterns using the inter-ocular displacements for controlling exposures of each SLM imaging unit; and compensating for imperfections in alignment of the plurality of SLM imaging units.

5. The method of claim 1 , wherein assigning one or more SLM imaging units further comprises:

performing rotational factor corrections on the plurality of partitioned mask data patterns in accordance with the plurality of SLM imaging units, wherein each of the partitioned mask data pattern has a corresponding rotational factor correction, and wherein performing rotational factor corrections comprises detecting rotational errors of the plurality of SLM imaging units, measuring the rotational corrections factors for each SLM imaging unit in the plurality of SLM imaging units, and calibrating the plurality of partitioned mask data patterns to control exposures by the plurality of SLM imaging units.

6. The method of claim 1 , wherein assigning one or more SLM imaging units further comprises:

performing substrate deformation corrections on the plurality of partitioned mask data patterns in accordance with the plurality of SLM imaging units, wherein each of the partitioned mask data pattern has a corresponding substrate deformation correction.

7. The method of claim 1 , wherein controlling the plurality of SLM imaging units comprises:

for each SLM imaging unit, exposing a corresponding partitioned mask data pattern independent of other SLM imaging units in the image writer system.

8. A system for manufacturing a three-dimensional integrated circuit, comprising:

a plurality of spatial light modulator (SLM) imaging units arranged in one or more parallel arrays;

a controller configured to control the plurality of SLM imaging units, wherein the controller includes

logic for receiving mask data to be written to one or more layers of the three-dimensional integrated circuit;

logic for processing the mask data to form a plurality of partitioned mask data patterns corresponding to the one or more layers of the three-dimensional integrated circuit, wherein the logic for processing the mask data comprises arranging a placement of one or more layout blocks in the one or more layers of the three-dimensional integrated circuit, and logic for identifying through silicon vias for routing communication signals between the one or more layout blocks in the one or more layers of the three-dimensional integrated circuit;

logic for assigning one or more SLM imaging units to handle each of the partitioned mask data pattern; and

logic for controlling the plurality of SLM imaging units to write the plurality of partitioned mask data patterns to the one or more layers of the three-dimensional integrated circuits in parallel.

9. The system of claim 8 , wherein logic for assigning one or more SLM imaging units comprises:

logic for performing scaling corrections on the plurality of partitioned mask data patterns in accordance with the plurality of SLM imaging units, wherein each of the partitioned mask data pattern has a corresponding scaling correction.

10. The system of claim 8 , wherein logic for assigning one or more SLM imaging units further comprises:

logic for performing alignment corrections on the plurality of partitioned mask data patterns in accordance with the plurality of SLM imaging units, wherein each of the partitioned mask data pattern has a corresponding alignment correction.

11. The system of claim 8 , wherein logic for assigning one or more SLM imaging units further comprises:

logic for performing inter-ocular displacement corrections on the plurality of partitioned mask data patterns in accordance with the plurality of SLM imaging units, wherein each of the partitioned mask data pattern has a corresponding inter-ocular displacement correction.

12. The system of claim 8 , wherein logic for assigning one or more SLM imaging units further comprises:

logic for performing rotational factor corrections on the plurality of partitioned mask data patterns in accordance with the plurality of SLM imaging units, wherein each of the partitioned mask data pattern has a corresponding rotational factor correction.

13. The system of claim 8 , wherein logic for assigning one or more SLM imaging units further comprises:

logic for performing substrate deformation corrections on the plurality of partitioned mask data patterns in accordance with the plurality of SLM imaging units, wherein each of the partitioned mask data pattern has a corresponding substrate deformation correction.

14. The system of claim 8 , wherein logic for controlling the plurality of SLM imaging units comprises:

for each SLM imaging unit, logic for exposing a corresponding partitioned mask data pattern independent of other SLM imaging units in the image writer system.

15. A method of manufacturing using partial wafers, comprising:

providing an imaging writer system, wherein the imaging writer system includes a plurality of spatial light modulator (SLM) imaging units arranged in one or more parallel arrays;

providing one or more partial wafers to be manufactured;

receiving mask data to be written to substrates of the one or more partial wafers;

processing the mask data to form a plurality of partitioned mask data patterns corresponding to the substrates of the one or more partial wafers;

assigning one or more SLM imaging units to handle each of the partitioned mask data pattern, wherein the assigning performs at least one of scaling, alignment, inter-ocular displacement, rotational factor, or substrate deformation correction, wherein assigning one or more SLM imaging units to handle each of the partitioned mask data pattern comprises performing alignment corrections on the plurality of partitioned mask data patterns in accordance with the plurality of SLM imaging units, wherein each of the partitioned mask data pattern has a corresponding alignment correction and performing subsequent alignment corrections in multiple exposures of the partitioned mask data pattern; and

controlling the plurality of SLM imaging units to write the plurality of partitioned mask data patterns to the substrates of the one or more partial wafers in parallel.

16. A method for manufacturing multiple designs on a printed circuit board (PCB) in parallel, comprising:

providing an imaging writer system, wherein the imaging writer system includes a plurality of spatial light modulator (SLM) imaging units arranged in one or more parallel arrays;

providing a printed circuit board, wherein the printed circuit board is partitioned into multiple regions, and each region holds a design to be manufactured;

receiving mask data to be written to the multiple regions of the printed circuit board;

processing the mask data to form a plurality of partitioned mask data patterns corresponding to the multiple regions of the printed circuit board;

assigning one or more SLM imaging units to handle each of the partitioned mask data pattern, wherein the assigning performs at least one of scaling, alignment, inter-ocular displacement, rotational factor, or substrate deformation correction, wherein assigning one or more SLM imaging units to handle each of the partitioned mask data pattern comprises performing alignment corrections on the plurality of partitioned mask data patterns in accordance with the plurality of SLM imaging units, wherein each of the partitioned mask data pattern has a corresponding alignment correction and performing subsequent alignment corrections in multiple exposures of the partitioned mask data pattern; and

controlling the plurality of SLM imaging units to write the plurality of partitioned mask data patterns to the multiple regions of the printed circuit board in parallel.