IP Library Granted Patent US 9,507,271
Granted Patent B1
US 9,507,271 · App. 13/225,405 · Granted Nov 29, 2016

System and method for manufacturing multiple light emitting diodes in parallel

Inventors: Jang Fung Chen (Cupertino, CA); Thomas Laidig (Richmond, CA)
Assignee: Applied Materials, Inc.
G03F7/70433G03F7/70275G03F7/70475G03F7/70508G03F7/70391
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Quick Facts
Patent No.
US 9,507,271
App. No.
13/225,405
Granted
Nov 29, 2016
Kind
B1
Abstract

System and method for manufacturing multiple light emitting diodes in parallel are disclosed. In one embodiment, the method includes providing an imaging writer system that includes a plurality of spatial light modulator (SLM) imaging units arranged in one or more parallel arrays, providing one or more substrates corresponding to multiple LEDs to be manufactured, receiving mask data to be written to the one or more substrates corresponding to the multiple LEDs, processing the mask data to form a plurality of partitioned mask data patterns corresponding to the plurality substrates of the multiple LEDs, assigning one or more SLM imaging units to handle each of the partitioned mask data pattern, and controlling the plurality of SLM imaging units to write the plurality of partitioned mask data patterns to the plurality substrates of the multiple LEDs in parallel.

Claims (49)

1. A method for manufacturing multiple light emitting diodes (LEDs) in parallel, comprising:

providing an imaging writer system, wherein the imaging writer system includes a plurality of spatial light modulator (SLM) imaging units arranged in one or more parallel arrays;

providing a plurality of light emitting diode (LED) wafers to be manufactured;

receiving mask data to be written to the plurality of LED wafers;

processing the mask data to form a plurality of partitioned mask data patterns corresponding to the plurality of LED wafers, wherein processing the mask data to form the plurality of partitioned mask data patterns corresponding to the plurality of LED wafers comprises scaling the plurality of LED wafers from a first wafer size to a second wafer size, wherein the first wafer size is smaller than the second wafer size;

assigning one or more SLM imaging units to handle each of the partitioned mask data pattern; and

controlling the plurality of SLM imaging units to write the plurality of partitioned mask data patterns to the plurality of LED wafers in parallel, wherein the controlling the plurality of SLM imaging units comprises compensating for wafer warp caused by the scaling of the plurality of LED wafer from the first wafer size to the second wafer size.

2. The method of claim 1 , wherein processing the mask data comprises:

processing the mask data to form a plurality of partitioned mask data patterns corresponding to the plurality LED wafers of a same LED design.

3. The method of claim 1 , wherein processing the mask data comprises:

processing the mask data to form a plurality of partitioned mask data patterns corresponding to the plurality LED wafers of different LED designs.

4. The method of claim 1 , wherein controlling the plurality of SLM imaging units comprises:

detecting deformation at each local region of a LED wafer in the plurality of LED wafers associated with each SLM imaging unit; and

adjusting focus at each SLM imaging unit in response to the deformation at each local region of the LED wafer in the plurality of LED wafers.

5. The method of claim 1 , wherein controlling the plurality of SLM imaging units further comprises:

detecting rotational errors at each local region of a LED wafer in the plurality of LED wafers associated with each SLM imaging unit;

determining rotational correction factors to the corresponding partitioned mask data pattern; and

applying the rotational correction factors to the corresponding partitioned mask data pattern for each local region of the LED wafer in the plurality of LED wafers associated with each SLM imaging unit.

6. The method of claim 1 , wherein controlling the plurality of SLM imaging units further comprises:

detecting pattern distortions due to substrate deformation at each local region of a LED wafer in the plurality of LED wafers associated with each SLM imaging unit;

determining pattern correction factors to the corresponding partitioned mask data pattern; and

applying the pattern correction factors to the corresponding partitioned mask data pattern for each local region of the LED wafer in the plurality of LED wafers associated with each SLM imaging unit.

7. The method of claim 1 , wherein providing the plurality of LED wafers to be manufactured comprises:

depositing a thin film of gallium nitride on a sapphire wafer via a metal organic chemical vapor deposition, wherein the thin film of gallium nitride is configured to resist film cracking, and wherein the thin film of gallium nitride causes warping of the each LED wafer in the plurality of LED wafers.

8. A system for manufacturing multiple light emitting diodes (LEDs) in parallel, comprising:

a plurality of spatial light modulator (SLM) imaging units arranged in one or more parallel arrays;

a controller configured to control the plurality of SLM imaging units, wherein the controller includes

logic for providing a plurality of light emitting diode (LED) wafers to be manufactured;

logic for receiving mask data to be written to the plurality of LED wafers;

logic for processing the mask data to form a plurality of partitioned mask data patterns corresponding to the plurality of LED wafers, wherein the logic for processing the mask data to form the plurality of partitioned mask data patterns corresponding to the plurality of LED wafers comprises logic for scaling the plurality of LED wafer from a first wafers size to a second wafer size, wherein the first wafer size is smaller than the second wafer size;

logic for assigning one or more SLM imaging units to handle each of the partitioned mask data pattern; and

logic for controlling the plurality of SLM imaging units to write the plurality of partitioned mask data patterns to the plurality of LED wafers in parallel, wherein the logic for controlling the plurality of SLM imaging units comprises logic for compensating for wafer warp caused by the scaling of the plurality of LED wafer from the first wafer size to the second wafer size.

9. The system of claim 8 , wherein logic for processing the mask data comprises:

logic for processing the mask data to form a plurality of partitioned mask data patterns corresponding to the plurality LED wafers of a same LED design.

10. The system of claim 8 , wherein logic for processing the mask data comprises:

logic for processing the mask data to form a plurality of partitioned mask data patterns corresponding to the plurality LED wafers of different LED designs.

11. The system of claim 8 , wherein logic for controlling the plurality of SLM imaging units comprises:

logic for detecting deformation at each local region of a LED wafer in the plurality of LED wafers associated with each SLM imaging unit; and

logic for adjusting focus at each SLM imaging unit in response to the deformation at each local region of the LED wafer in the plurality of LED wafers.

12. The system of claim 8 , wherein logic for controlling the plurality of SLM imaging units further comprises:

logic for detecting rotational errors at each local region of a LED wafer in the plurality of LED wafers associated with each SLM imaging unit;

logic for determining rotational correction factors to the corresponding partitioned mask data pattern; and

logic for applying the rotational correction factors to the corresponding partitioned mask data pattern for each local region of the LED wafer in the plurality of LED wafers associated with each SLM imaging unit.

13. The system of claim 8 , wherein logic for controlling the plurality of SLM imaging units further comprises:

logic for detecting pattern distortions due to substrate deformation at each local region of a LED wafer in the plurality of LED wafers associated with each SLM imaging unit;

logic for determining pattern correction factors to the corresponding partitioned mask data pattern; and

logic for applying the pattern correction factors to the corresponding partitioned mask data pattern for each local region of the LED wafer in the plurality of LED wafers associated with each SLM imaging unit.

14. The system of claim 8 , wherein logic for providing the plurality of LED wafers to be manufactured comprises:

logic for depositing a thin film of gallium nitride on a sapphire wafer via a metal organic chemical vapor deposition, wherein the thin film of gallium nitride is configured to resist film cracking, and wherein the thin film of gallium nitride causes warping of the each LED wafer in the plurality of LED wafers.

Assignments (5)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 23, 2015
From: PINEBROOK IMAGING INC.
To: APPLIED MATERIALS, INC.
Reel/Frame 034797/0686 →
SECURITY INTEREST Recorded Apr 17, 2014
From: PINEBROOK IMAGING, INC.
To: APPLIED VENTURES, LLC
Reel/Frame 032712/0642 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 13, 2013
From: PINEBROOK IMAGING TECHNOLOGY, LTD.
To: PINEBROOK IMAGING, INC.
Reel/Frame 029984/0331 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 26, 2011
From: PINEBROOK IMAGING SYSTEMS CORPORATION
To: PINEBROOK IMAGING TECHNOLOGY, LTD.
Reel/Frame 027127/0782 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2011
From: CHEN, JANG FUNG; LAIDIG, THOMAS
To: PINEBROOK IMAGING SYSTEMS CORPORATION
Reel/Frame 027119/0299 →
Continuity (2)
Continuation In Part 12475114 · May 29, 2009
Provisional Application 61379734 · Sep 3, 2010