Advanced processor with mechanism for packet distribution at high line rate
An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
1. A processor, comprising:
a plurality of processor cores to execute multiple threads, each of the plurality of processor cores having an instruction cache and data cache;
a memory bridge to couple the plurality of processor cores to a memory external to the plurality of processor cores;
a packet distribution engine (PDE) to receive a plurality of packets from an input and to provide the plurality of packets to respective threads of the multiple threads;
a first ring-based interconnect to couple the PDE to the instruction caches of the plurality of processor cores and to provide a first data pathway from a respective processor core to each of the other processor cores via their corresponding instruction caches without going through the memory, wherein the PDE is external to the plurality of processor cores; and
a second ring-based interconnect to provide a second data pathway from the respective processor core to each of the other processor cores via their corresponding data caches without going through the memory.
2. The processor of claim 1 , wherein the first ring-based interconnect comprises a messaging network.
3. The processor of claim 1 , wherein the second ring-based interconnect comprises a data switch interconnect.
4. The processor of claim 1 , wherein the PDE is to provide the plurality of packets to the respective threads in a load-balanced distribution.
5. The processor of claim 4 , wherein the load-balanced distribution includes a round-robin distribution.
6. The processor of claim 4 , wherein the load-balanced distribution includes a weighted round-robin distribution.
7. The processor of claim 1 , wherein the plurality of processor cores comprises 8 processor cores.
8. The processor of claim 1 , wherein the multiple threads comprise 32 threads.
9. A method of controlling a flow of packets, the method comprising:
receiving a plurality of packets from an input;
providing the plurality of packets to a packet distribution engine (PDE);
executing multiple threads on respective processor cores of a plurality of processor cores, each of the processor cores having an instruction cache and a data cache;
distributing the plurality of packets from the PDE to respective threads of the multiple threads via a first ring-based interconnect that couples the PDE with the plurality of processor cores via their corresponding instruction cache, wherein the PDE is external to the plurality of processor cores;
passing first information among the plurality of processor cores via the first ring-based interconnect without the first information going through a memory external to the processor cores; and
passing second information among the plurality of processor cores via a second ring-based interconnect that couples the plurality of processor cores via their corresponding data caches, without the second information going through the memory external to the processor cores.
10. The method of claim 9 , wherein the first ring-based interconnect comprises a messaging network.
11. The method of claim 9 , wherein the second ring-based interconnect comprises a data switch interconnect.
12. The method of claim 9 , wherein the plurality of packets are distributed from the PDE to the respective threads in a load-balanced distribution.
13. The method of claim 12 , wherein the load-balanced distribution includes a round-robin distribution.
14. The method of claim 12 , wherein the load-balanced distribution includes a weighted round-robin distribution.
15. The method of claim 12 , wherein the multiple threads comprise 32 threads.
16. The method of claim 12 , wherein the plurality of processor cores comprises 8 cores.
17. The method of claim 12 , wherein distributing the plurality of packets comprises insetting a packet descriptor into a message corresponding to at least one of the plurality of packets.
18. The method of claim 12 , wherein the passing the second information among the plurality of processor cores via the second ring-based interconnect comprises using a credit-based flow-control scheme.
19. The method of claim 18 , wherein using the credit-based flow-control scheme comprises guiding a distribution of at least one of the plurality of packets from a first thread to a second thread, wherein the multiple threads include the first and second threads.
20. The method of claim 19 , wherein the guiding is in response to determining that a pace of credit availability for the first thread is slower than a pace of credit availability for the second thread.