Monocrystalline semiconductor wafer comprising defect-reduced regions and method for producing it
View Patent ↗Monocrystalline semiconductor wafers have defect-reduced regions, the defect-reduced regions having a density of GOI-relevant defects within the range of 0/cm 2 to 0.1/cm 2 and occupy overall an areal proportion of 10% to 100% of the planar area of the semiconductor wafer, wherein the remaining regions of the semiconductor wafer have a significantly higher defect density than the defect-reduced regions. The wafers may be produced by a method for annealing GOI relevant defects in the wafer, by irradiating defined regions of a side of the semiconductor wafer by laser wherein each location is irradiated with a power density of 1 GW/m 2 to 10 GW/m 2 for at least 25 ms, wherein the laser emits radiation of a wavelength above the absorption edge of the wafer semiconductor material and wherein the temperature of the wafer rises by less than 20 K as a result of irradiation.
1. A monocrystalline semiconductor wafer having defect-reduced regions, wherein said defect-reduced regions have a density of GOI-relevant defects within the range of 0/cm 2 to 0.1/cm 2 and occupy overall an area proportion of 10% to 100% of the planar area of the semiconductor wafer, wherein remaining regions of the semiconductor wafer have a significantly higher defect density than the defect-reduced regions.
2. The monocrystalline semiconductor wafer of claim 1 , wherein the density of the GOI relevant defects in the remaining regions is at least twice as great as in the defect-reduced regions.
3. The monocrystalline semiconductor wafer of claim 1 , wherein the density of the GOI relevant defects deviates at arbitrary locations within the defect-reduced regions by at most 10% from the average value of the density of the GOI relevant defects that is determined in the defect-reduced regions.
4. The monocrystalline semiconductor wafer of claim 1 , wherein the defect-reduced regions extend over the entire thickness of the semiconductor wafer.
5. The monocrystalline semiconductor wafer of claim 3 , wherein the defect-reduced regions extend over the entire thickness of the semiconductor wafer.
6. The monocrystalline semiconductor wafer of claim 1 , wherein the defect-reduced regions occupy an area proportion of 95% to 100% of the planar area of the semiconductor wafer.
7. The monocrystalline semiconductor wafer of claim 3 , wherein the defect-reduced regions occupy an area proportion of 95% to 100% of the planar area of the semiconductor wafer.
8. The monocrystalline semiconductor wafer of claim 4 , wherein the defect-reduced regions occupy an area proportion of 95% to 100% of the planar area of the semiconductor wafer.
9. The monocrystalline semiconductor wafer as claimed claim 1 , wherein the defect-reduced regions occupy an area proportion of 10% to 95% of the planar area of the semiconductor wafer.
10. The monocrystalline semiconductor wafer of claim 1 , wherein the density of the GOI relevant defects changes abruptly at the boundaries between the defect-reduced regions and the remaining regions of the semiconductor wafer.
11. The monocrystalline semiconductor wafer of claim 10 , wherein the density of the GOI relevant defects changes by at least a factor of 2 at the boundaries between the defect-reduced regions and the remaining regions along a section having a length of 0.5 mm that runs parallel to the planar areas of the semiconductor wafer and perpendicular to the respective boundary.
12. The monocrystalline semiconductor wafer of claim 1 , which comprises at least 80% silicon.
13. The monocrystalline semiconductor wafer of claim 5 , wherein the defect-reduced regions occupy an areal proportion of 95% to less than 100% of the planar area of the semiconductor wafer.