IP Library Granted Patent US 8,619,024
Granted Patent B2
US 8,619,024 · App. 13/230,272 · Granted Dec 31, 2013

Automated system and method for high-frequency signal attenuation compensation

Inventor: David Hoerl (Warren, NJ)
Assignee: RIIP, Inc.
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Quick Facts
Patent No.
US 8,619,024
App. No.
13/230,272
Granted
Dec 31, 2013
Kind
B2
Abstract

Disclosed is a high-frequency boost circuitry for use with a computer management system. Detection circuitry at the receiving end of a video signal measures the amplitudes of various frequency components of the video signal. If the amplitudes of the high-frequency components of the video signal are substantially lower than the amplitudes of the low frequency components of the video signal, the detection circuitry sends the amplitude information to analysis circuitry located at the transmitting end of the video signal. The analysis circuitry utilizes this information to determine the appropriate level of amplification needed for the video signal. This results in improved signal to noise ratio at the receiver in the computer management system.

Claims (14)

1. A user station comprising:

a) a video signal entry circuit carrying an uncompensated video signal;

b) a video processing system having

i) a video compensation circuit coupled to the video signal entry circuit,

ii) a level shift circuit coupled to the video compensation circuit,

iii) a zero volt clip circuit coupled to the level shift circuit,

iv) an integration circuit coupled to the zero volt clip circuit,

v) a sample and hold circuit coupled to the integration circuit,

vi) a signal conditioning circuit coupled to the sample and hold circuit,

vii) an analog to digital converter coupled to the sample and hold circuit,

viii) a processor coupled to the sample and hold circuit and to the video compensation circuit,

ix) a timing detection circuit coupled to the video signal entry circuit,

x) a control pulse generation circuit coupled to the integration circuit, and coupled to the sample and hold circuit; and

c) the timing detection circuit having a DC restoration circuit coupled to a fast comparator circuit, a synch extractor circuit coupled to a logic circuit in turn coupled to the DC restoration circuit, the fast comparator circuit is also coupled to the control pulse generation circuit.

Assignments (3)
RELEASE OF SECURITY INTEREST Recorded Oct 8, 2015
From: PNC BANK NATIONAL ASSOCIATION
To: RARITAN INC; RARITAN AMERICAS, INC.,; RARITAN TECHNOLOGIES, INC.,; RIIP, INC.
Reel/Frame 036819/0205 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 30, 2013
From: HOERL, DAVID
To: RIIP, INC.
Reel/Frame 031120/0372 →
SECURITY AGREEMENT Recorded Sep 10, 2012
From: RARITAN, INC.; RARITAN AMERICAS, INC.; RARITAN TECHNOLOGIES, INC.; RIIP, INC.
To: PNC BANK, NATIONAL ASSOCIATION
Reel/Frame 028924/0527 →
Continuity (2)
Continuation 10740381 · Dec 17, 2003
Related Publication 20120026401A1 · Feb 2, 2012