Structure and process for the formation of TSVs
An integrated circuit structure includes a semiconductor substrate; an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD); an opening penetrating the interconnect structure into the semiconductor substrate; a conductor in the opening; and an isolation layer having a vertical portion and a horizontal portion physically connected to each other. The vertical portion is on sidewalls of the opening. The horizontal portion is directly over the interconnect structure. The integrated circuit structure is free from passivation layers vertically between the top IMD and the horizontal portion of the isolation layer.
1. An integrated circuit structure comprising:
a semiconductor substrate;
an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD);
an opening penetrating the interconnect structure into the semiconductor substrate;
a conductor in the opening;
an isolation layer contacting a top surface of the top IMD and lining sidewalls of the opening; and
a top metal pad having a top surface no lower than a top surface of the top IMD, with no metal layer vertically between the top IMD and the top metal pad, the top metal pad connected to a metal line overlying the conductor.
2. The integrated circuit structure of claim 1 , wherein the metal line and the conductor comprise same materials and form a continuous region.
3. The integrated circuit structure of claim 2 , wherein the top metal pad is over the top IMD.
4. The integrated circuit structure of claim 3 , wherein the isolation layer overlaps edge portions of the top metal pad.
5. The integrated circuit structure of claim 2 , wherein the top metal pad is in the top IMD, and wherein the metal line extends down to contact the top metal pad through an additional opening in the isolation layer.
6. The integrated circuit structure of claim 5 , wherein the top metal pad comprises copper.
7. The integrated circuit structure of claim 2 , wherein the metal line includes copper.
8. The integrated circuit structure of claim 1 , wherein the integrated circuit structure is free from silicon nitride between the top IMD and a horizontal portion of the isolation layer.
9. The integrated circuit structure of claim 1 , wherein the isolation layer comprises a layer selected from the group consisting essentially of an oxide layer, a nitride layer, and a composite layer comprising a nitride sub-layer on an oxide sub-layer.
10. The integrated circuit structure of claim 1 , wherein the top IMD comprises a material selected from the group consisting essentially of un-doped silicate glass, fluorinated silicate glass, low-k dielectric material, black diamond, and combinations thereof.
11. The integrated circuit structure of claim 1 , wherein the conductor includes a diffusion barrier layer.
12. The integrated circuit structure of claim 1 , wherein the conductor includes a copper seed layer.
13. An integrated circuit structure comprising:
a semiconductor substrate;
an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD);
a top metal pad in the top IMD and having a top surface substantially level with a top surface of the top IMD;
an opening extending through the interconnect structure and into the semiconductor substrate;
a conductor in the opening; and
an isolation layer disposed on a portion of the top surface of the top IMD and lining sidewalls of the opening, and wherein the isolation layer comprises an additional opening exposing the top metal pad.
14. The integrated circuit structure of claim 13 , wherein the conductor extends down into the additional opening in the isolation layer to physically contact the top metal pad.
15. The integrated circuit structure of claim 13 , wherein the isolation layer comprises a silicon nitride layer on a silicon oxide layer.
16. The integrated circuit structure of claim 13 , wherein the top IMD is a low-k dielectric layer.
17. The integrated circuit structure of claim 13 , wherein the top metal pad is connected to a metal line overlying the conductor, and wherein the metal line and the conductor comprise same materials and form a continuous region.
18. An integrated circuit structure comprising:
a semiconductor substrate;
an interconnect structure over the semiconductor substrate, wherein the interconnect structure comprises a top inter-metal dielectric (IMD);
a top metal pad over the top IMD;
a conductor formed in an opening extending through the interconnect structure and into the semiconductor substrate;
an isolation layer covering a portion of the top IMD and lining sidewalls of the opening; and
a continuous metal feature extending into the opening to form a TSV, and wherein the continuous metal feature contacts the conductor.
19. The integrated circuit structure of claim 18 , wherein the top metal pad comprises aluminum.
20. The integrated circuit structure of claim 18 , wherein the continuous metal feature extends down into an additional opening in the isolation layer to physically contact the top metal pad.