Semiconductor device and wafer

1. A semiconductor device, comprising:

a semiconductor substrate;

a plurality of LSI regions that are formed on the semiconductor substrate and are provided with a first power supply wiring layer including a first power supply wire;

a first power supply terminal formed on the semiconductor substrate;

a second power supply wiring layer including a second power supply wire that electrically connects the first power supply wire and the first power supply terminal, the second power supply wiring layer is formed in a dicing region between the LSI regions along a dicing line that separates the LSI regions and the dicing line region; and

a second power supply terminal formed on the semiconductor substrate,

wherein a first barrier metal film is formed at least in the LSI regions at a boundary between the first power supply wire and the second power supply wire,

wherein the first power supply wiring layer further includes a third power supply wire,

the second power supply wiring layer further includes a fourth power supply wire that is formed below the second power supply wire and electrically connects the third power supply wire and the second power supply terminal,

wherein a second barrier metal film is formed at least in the LSI regions at a boundary between the third power supply wire and the fourth power supply wire.

2. The semiconductor device according to claim 1 , further comprising:

a voltage generating circuit that is formed on the semiconductor substrate, generates a voltage based on a voltage applied to the first power supply terminal and outputs the generated voltage to the fourth power supply wire.

3. The semiconductor device according to claim 1 , wherein the first and second barrier metal films are made of TaN.

4. The semiconductor device according to claim 1 , wherein a first testing voltage is applied to the first power supply terminal for a test, the first testing voltage being supplied to the first power supply wire through the third power supply wire.

5. The semiconductor device according to claim 1 ,

wherein each of the plurality of LSI regions further includes a wire bonding pad, and

wherein the first power supply wire is electrically connected to the wire bonding pad.

6. The semiconductor device according to claim 1 ,

wherein each of the plurality of LSI regions further includes a plurality of wire bonding pads, and

wherein the first power supply wire is electrically connected to the plurality of wire bonding pads commonly.

7. The semiconductor device according to claim 1 ,

wherein each of the plurality of LSI regions further includes a plurality of wire bonding pads, and

wherein the third power supply wire is electrically connected to the plurality of wire bonding pads commonly.

8. The semiconductor device according to claim 1 ,

wherein each of the plurality of LSI regions further includes a plurality of wire bonding pads,

wherein the first power supply wire is electrically connected to a plurality of first wire bonding pads of the plurality of wire bonding pads, and

wherein the second power supply wire is electrically connected to a plurality of second wire bonding pads of the plurality of wire bonding pads.

9. The semiconductor device according to claim 1 , wherein a width of the dicing line region between adjacent LSI regions is smaller than twice the width of the first and second power supply wires extending between the adjacent LSI regions.