LED display systems
An LED display system comprises an LED array and an LED driver circuit. An LED driver circuit comprises components including a phase lock loop, a pulse width modulation engine, a configuration register, a series of gain adjustable fast charge current sources, and a serial input/output interface. The components in this driver circuit may be integrated on a same chip. The LED array may be arranged in a common cathode configuration.
1. A method of driving LEDs, comprising the steps of:
connecting an array of LEDs to an integrated driver circuit,
wherein the integrated driver circuit comprises a phase lock loop, a plurality of pulse width modulation engines, a configuration register, a plurality of gain adjustable fast charge current sources, and a serial input/output interface,
wherein the LED array comprises columns of red, green, and blue LEDs having their anodes connected to red, green, and blue common anode nodes respectively, and the integrated driver circuit comprises a plurality of power sources;
operatively connecting a power source to a common anode node;
setting the voltage of the power source connected to a red common anode node at 1.8 volts to 2.6 volts; and
setting the voltage of the power source connected to a green common anode node or a blue common anode node at 2.6 volts to 3.8 volts;
providing a global clock signal with the phase lock loop;
storing driver circuit settings in a SRAM;
loading driver circuit settings into the configuration register;
loading gray scale values and the global clock signal to the pulse width modification engine;
generating PWM signals for the plurality of gain adjustable fast charge current sources;
loading DOT correction settings into a memory within a gain adjustable fast charge current source circuit; and
providing a stable current to the LEDs based on pulse-width modification engines output signal.
2. The method of claim 1 , wherein the integrated driver circuit further comprises a sink current return circuit for receiving a current from the LED array.
3. The method of claim 1 , wherein the integrated driver circuit further comprises an error detection circuit, wherein the error detection circuit monitors the current output from one or more of the plurality of gain adjustable fast charge current sources for detecting a short circuit status.
4. The method of claim 1 , wherein one or more of the plurality of pulse width modulation engines comprises a skew control for displacing a rising edge of the current output, a counter, a SRAM that stores a gray scale data and a dot correction data, a gray scale loading circuit, and an comparator for generating the PWM signal.
5. The method of claim 2 , wherein the sink current return circuit comprises a ghost elimination circuit.
6. The method of claim 1 , wherein the phase lock loop comprises an internal global clock or receives an external global clock signal.
7. The method of claim 1 , wherein the power source operatively connected to the red common anode node provides a voltage of 1.8 volts to 2.4 volts.
8. The method of claim 1 , wherein the power source operatively connected to the blue common anode node or the green common anode node provides a voltage of 2.6 volts to 3.6 volts.