Drive circuit for display panel, and display device

1. A drive circuit for driving a display panel including a plurality of pixels, the drive circuit comprising:

a plurality of unit drive circuits which are provided for respective groups formed by dividing the plurality of pixels, each unit drive circuit outputting a drive signal which becomes a first potential at the time of driving the group of pixels and becomes a second potential at the time of non-driving the group of pixels during a common control period among the groups of pixels; and

first to n-th power source circuits (n being a natural number of 2 or more) each of which selectively outputs a third potential which is an intermediate potential between the first potential and the second potential and the second potential,

each unit drive circuit comprising:

a selective pulse output circuit which outputs a selective pulse having the first potential during an outputting operation period set sequentially in the control period for every group of pixels; and

a k-th output terminal switch which is comprised of a transistor and which establishes or interrupts the connection between an output terminal of the unit drive circuit and the k-th power source circuit (k being an integer satisfying 1≦k≦n),

wherein at least one of the first to n-th output terminal switches is brought into an ON state, and the output terminal switches are alternately brought into an OFF state during the control period other than the outputting operation period, and

wherein the k-th power source circuit is configured to output only the second potential which is inputted to a source of the k-th output terminal switch during a period where the k-th output terminal switch is in an ON state and to output the third potential which is inputted to the source of the k-th output terminal switch within at least a portion of a period where the k-th output terminal switch is in an OFF state.

2. The drive circuit according to claim 1 , wherein the selective pulse output circuit includes a transistor which is turned on when the first potential is applied to a gate terminal thereof and is turned off when the second potential is applied to the gate terminal thus establishing or interrupting the connection between a clock signal line and the output terminal, and outputs the selective pulse in response to a clock pulse from the clock signal line by turning on the transistor during the outputting operation period,

wherein the unit drive circuit further includes a k-th gate terminal switch which is formed of a transistor and establishes or interrupts the connection between the gate terminal and the k-th power source circuit, and

wherein the k-th gate terminal switch is operated in synchronism with the k-th output terminal switch.

3. The drive circuit according to claim 1 , wherein the output terminal switch is formed of an amorphous silicon thin film transistor.

4. The drive circuit according to claim 2 , wherein the gate terminal switch is formed of an amorphous silicon thin film transistor.

5. The drive circuit according to claim 1 , wherein the third potential is a ground potential of the drive circuit.

6. An image display device comprising:

the drive circuit described in claim 1 ; and

a display panel driven using the drive circuit.

7. A drive circuit for driving a display panel including a plurality of pixels, the drive circuit comprising:

a plurality of unit drive circuits which are provided for respective groups formed by dividing the plurality of pixels, each unit drive circuit outputting a drive signal whose potential is changed over between at the time of driving the group of pixels and at the time of non-driving the group of pixels during a common control period among the groups of pixels; and

first to n-th power source circuits (n being a natural number of 2 or more) each of which selectively outputs a third potential which is an intermediate potential between a first potential and a second potential and the second potential,

each unit drive circuit comprising:

a selective pulse output circuit which includes a transistor which is turned on when the first potential is applied to a gate terminal thereof and is turned off when the second potential is applied to the gate terminal thus establishing or interrupting the connection between a clock signal line and an output terminal of the unit drive circuit, and outputs a selective pulse to the drive signal in response to a clock pulse from the clock signal line by turning on the transistor during an output operation period set sequentially during the control period for every group of pixels; and

a k-th gate terminal switch which is comprised of a transistor and which establishes or interrupts the connection between the gate terminal of the transistor and the k-th power source circuit (k being an integer satisfying 1≦k≦n),

wherein at least one of the first to n-th gate terminal switches is brought into an ON state, and the gate terminal switches are alternately brought into an OFF state during the control period other than the outputting operation period, and

wherein the k-th power source circuit is configured to output only the second potential which is inputted to a source of the k-th gate terminal switch during a period where the k-th gate terminal switch is in an ON state and to output the third potential which is inputted to the source of the k-th gate terminal switch within at least a portion of a period where the k-th gate terminal switch is in an OFF state.

8. The drive circuit according to claim 7 , wherein the gate terminal switch is formed of an amorphous silicon thin film transistor.

9. The drive circuit according to claim 7 , wherein the third potential is a ground potential of the drive circuit.

10. An image display device comprising:

the drive circuit described in claim 7 ; and

a display panel driven using the drive circuit.