Bump structure including nano-wires and a body connecting ends of the nano-wires, semiconductor package having the bump structure and method of manufacturing the semiconductor package
Provided are a bump structure includes a first bump and a second bump, a semiconductor package including the same, and a method of manufacturing the same. The bump structure includes: first bump provided on a connection pad of a substrate, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and a second bump provided on the body of the first bump.
1. A bump structure of a semiconductor package, the bump structure comprising:
a first bump on a connection pad of a substrate of the semiconductor package, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and
a second bump directly on the body of the first bump and adhered to another connection pad.
2. The bump structure of claim 1 , further comprising a template having nano-sized openings on the connection pad, wherein the plurality of nano-wires extend from the nano-sized openings of the template, respectively.
3. The bump structure of claim 2 , wherein portions of the plurality of nano-wires extrude from the nano-sized openings of the template, and an end of the second bump surrounds the portions of the plurality of nano-wires.
4. The bump structure of claim 2 , wherein the template comprises anodized aluminum oxide (AAO).
5. The bump structure of claim 2 , wherein the template comprises a polymer.
6. The bump structure of claim 1 , wherein the plurality of nano-wires is integrally provided with the body.
7. The bump structure of claim 1 , wherein the plurality of nano-wires is arranged regularly on the connection pad.
8. The bump structure of claim 1 , wherein the first bump has a height of about 1 μm to about 50 μm.
9. The bump structure of claim 1 , wherein a nano-wire, of the plurality of nano-wires, has a thickness of about 10 nm to about 100 nm.
10. A semiconductor package, comprising:
a semiconductor chip;
a mounting substrate to mount the semiconductor chip;
a first bump on a connection pad of the semiconductor chip, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires; and
a second bump directly on the body of the first bump, the second bump adhered to a connection pad of the mounting substrate.
11. The semiconductor package of claim 10 , further comprising a template having nano-sized openings on the connection pad of the semiconductor chip, wherein the plurality of nano-wires extend from the nano-sized openings of the template, respectively.
12. The semiconductor package of claim 11 , wherein the template comprises anodized aluminum oxide (AAO).
13. The semiconductor package of claim 11 , wherein the template comprises a polymer.
14. The semiconductor package of claim 10 , wherein the plurality of nano-wires is integrally provided with the body.
15. The semiconductor package of claim 10 , wherein the plurality of nano-wires is arranged regularly on the connection pad of the semiconductor chip.
16. The semiconductor package of claim 10 , wherein the connection pad of the semiconductor chip is a plug that penetrates the semiconductor chip.
17. The semiconductor package of claim 16 , further comprising at least one semiconductor device, wherein the at least one semiconductor device is electrically connected to the semiconductor chip by the plug.
18. The semiconductor package of claim 17 , wherein:
a semiconductor device, of the at least one semiconductor device, is electrically connected to the semiconductor chip by a bump structure;
the bump structure having a first end connected to a device connection pad of the semiconductor device, and a second end adhered to a plug connection pad on the plug; and
the bump structure including a plurality of nano-wires extending from the device connection pad and a body connecting end portions of the plurality of nano-wires.
19. The semiconductor package of claim 10 , further comprising a redistribution plate between the mounting substrate and the semiconductor chip, wherein the redistribution plate is electrically connected to at least one of the mounting substrate and the semiconductor chip by the first bump and the second bump.
20. A bump structure of a semiconductor package, the bump structure comprising:
a first bump having a first end connected to a connection pad of a substrate of the semiconductor package, the first bump including a plurality of nano-wires extending from the connection pad and a body connecting end portions of the plurality of nano-wires,
wherein the plurality of nano-wires is integrally provided with the body.
21. The bump structure of claim 20 , wherein a second end of the first bump, opposite the first end, is connected to another connection pad of the semiconductor package.
22. The bump structure of claim 20 , further comprising a template having nano-sized openings on the connection pad, wherein the plurality of nano-wires extend from the nano-sized openings of the template, respectively.