Semiconductor memory device
According to one embodiment, a semiconductor memory device includes a plurality of memory cells each of which is arranged at the intersection position between a pair of complementary bit lines and a word line, and stores data between a first power supply voltage applied to a first node and a voltage applied to a virtual ground node, and a control circuit which changes the amount of current of the pair of bit lines in accordance with the amplitude of the pair of bit lines for each column in a memory macro, that is formed by arranging the plurality of memory cells in a matrix, in the data read operation of each of the plurality of memory cells.
1. A semiconductor memory device comprising:
a plurality of memory cells each of which is arranged at an intersection position between a pair of complementary bit lines and a word line, and configured to store data between a first power supply voltage applied to a first node and a voltage applied to a virtual ground node; and
a limiter which has an input and an output interposed between the virtual ground node and a second power supply node, and control terminals connected to the pair of bit lines, and is configured to monitor an amplitude of the pair of bit lines to limit a current path to the second power supply voltage when a sufficient amplitude is generated on the pair of bit lines.
2. The device of claim 1 , further comprising a power supply booster configured to monitor the amplitude of the pair of bit lines, and perform switching so as to boost the first power supply voltage applied to the first node of the memory cell having an insufficient bit line amplitude in data read.
3. The device of claim 1 , wherein the limiter includes a first transistor having a gate connected to one of the pair of bit lines, and a second transistor having a gate connected to the other of the pair of bit lines, the first transistor and the second transistor having current paths connected in series between the virtual ground node and the second power supply voltage.
4. The device of claim 1 , wherein the limiter includes a third transistor having a gate connected to one of the pair of bit lines, and a fourth transistor having a gate connected to the other of the pair of bit lines, the third transistor and the fourth transistor having current paths connected in parallel between the virtual ground node and the second power supply voltage.
5. The device of claim 1 , wherein the limiter includes:
a fifth transistor having a gate connected to one of the pair of bit lines, and a sixth transistor having a gate connected to the other of the pair of bit lines, the fifth transistor and the sixth transistor having current paths connected in series between the virtual ground node and the second power supply voltage; and
a seventh transistor having a gate connected to said other of the pair of bit lines, and an eighth transistor having a gate connected to said one of the pair of bit lines, the seventh transistor and the eighth transistor having current paths connected in series between the virtual ground node and the second power supply voltage.
6. The device of claim 2 , wherein the power supply booster includes:
a NAND circuit configured to input potential signals of the pair of bit lines, and output a boost signal corresponding to an input pre-sense signal;
an inverter circuit configured to invert and output the input boost signal;
a first switching element which has a back gate applied with the first power supply voltage, a current path with one end applied with the first power supply voltage, and the other end electrically connected to the first node, and a gate connected to the inverter circuit; and
a second switching element which has a back gate applied with a power supply voltage higher or lower than the first power supply voltage, a current path with one end applied with the power supply voltage higher or lower than the first power supply voltage, and the other end electrically connected to the first node, and a gate connected to the inverter circuit.
7. The device of claim 1 , wherein in a memory macro formed by arranging the plurality of memory cells in a matrix, the limiter and the power supply booster are arranged at each of two ends of each column, arranged for said each column, or arranged for each set of the plurality of memory cells.
8. A semiconductor memory device comprising:
a plurality of memory cells each of which is arranged at an intersection position between a pair of complementary bit lines and a word line, and configured to store data between a first power supply voltage applied to a first node and a voltage applied to a virtual ground node; and
a control circuit configured to change an amount of current of the pair of bit lines in accordance with an amplitude of the pair of bit lines for each column in a memory macro, that is formed by arranging the plurality of memory cells in a matrix, in a data read operation of each of the plurality of memory cells.
9. The device of claim 8 , wherein the control circuit comprises a limiter which has an input and an output interposed between the virtual ground node and a second power supply node, and control terminals connected to the pair of bit lines, and is configured to monitor the amplitude of the pair of bit lines to limit a current path to the second power supply voltage when a sufficient amplitude is generated on the pair of bit lines.
10. The device of claim 8 , wherein the control circuit comprises a power supply booster configured to monitor the amplitude of the pair of bit lines, and perform switching so as to boost the first power supply voltage applied to the first node of the memory cell having an insufficient bit line amplitude in data read.
11. The device of claim 9 , wherein the limiter includes a first transistor having a gate connected to one of the pair of bit lines, and a second transistor having a gate connected to the other of the pair of bit lines, the first transistor and the second transistor having current paths connected in series between the virtual ground node and the second power supply voltage.
12. The device of claim 9 , wherein the limiter includes a third transistor having a gate connected to one of the pair of bit lines, and a fourth transistor having a gate connected to the other of the pair of bit lines, the third transistor and the fourth transistor having current paths connected in parallel between the virtual ground node and the second power supply voltage.
13. The device of claim 9 , wherein the limiter includes:
a fifth transistor having a gate connected to one of the pair of bit lines, and a sixth transistor having a gate connected to the other of the pair of bit lines, the fifth transistor and the sixth transistor having current paths connected in series between the virtual ground node and the second power supply voltage; and
a seventh transistor having a gate connected to said other of the pair of bit lines, and an eighth transistor having a gate connected to said one of the pair of bit lines, the seventh transistor and the eighth transistor having current paths connected in series between the virtual ground node and the second power supply voltage.
14. The device of claim 10 , wherein the power supply booster includes:
a NAND circuit configured to input potential signals of the pair of bit lines, and output a boost signal corresponding to an input pre-sense signal;
an inverter circuit configured to invert and output the input boost signal;
a first switching element which has a back gate applied with the first power supply voltage, a current path with one end applied with the first power supply voltage, and the other end electrically connected to the first node, and a gate connected to the inverter circuit; and
a second switching element which has a back gate applied with a power supply voltage higher or lower than the first power supply voltage, a current path with one end applied with the power supply voltage higher or lower than the first power supply voltage, and the other end electrically connected to the first node, and a gate connected to the inverter circuit.
15. The device of claim 8 , wherein in a memory macro formed by arranging the plurality of memory cells in a matrix, the control circuit is arranged at each of two ends of each column, arranged for said each column, or arranged for each set of the plurality of memory cells.