Memory hard macro partition optimization for testing embedded memories

1. A circuit included in an embedded memory, the circuit comprising:

a functional input port, a functional output port, and a functional memory data path from the functional input port to the functional output port, the functional memory data path comprising:

an array of data buffer circuits including input latches located in peripheral memory circuitry included in a memory instance instantiated on a die,

an array of memory cells, and

an array of sense amplifiers included in the memory instance, the array of sense amplifiers including output latches located in the peripheral memory circuitry included in the memory instance;

a scan input port, a scan output port, and a scan data path from the scan input port to the scan output port, the scan data path comprising:

an array of scan flops, at least one scan flop in the array of scan flops comprising:

an input latch located in the peripheral memory circuitry, and

an additional output latch located in the in test logic separate from the memory instance, the additional output latch having an input coupled to the memory array and coupled to receive the output from the input latch located in the peripheral memory circuitry, the additional output latch having an output coupled to the scan output port;

wherein the scan output port of the scan data path bypasses the array of memory cells; and

a built-in self-test (BIST) input port, a BIST output port, and a BIST data path from the BIST input port to the BIST output port, the BIST input port operating as the functional input port when a BIST enable signal is set to a first logic level to enable transmission of functional data through BIST data path and operating in BIST mode when the BIST enable signal is set to a second logic level to enable transmission of BIST test data through the BIST data path, the BIST data path comprising:

at least one input latch from the input latches located in the peripheral memory circuitry;

the array of memory cells, and

at least one output latch from the output latches located in the peripheral memory circuitry included in the memory instance.

2. The circuit of claim 1 , wherein timing of functional memory data output from the functional output port is matched to timing of scan data output from the scan output port.

3. The circuit of claim 1 , wherein the input latches and output latches are clocked together.

4. The circuit of claim 1 further comprising a preload port, a serial test input port, a memory pipeline output port, and a serial test data path, the preload port configured to enable transmission through the serial test data path, the serial test data path comprising:

a BIST multiplexer circuit;

the at least one input latch from the array of data buffer circuits;

the array of memory cells;

a bypass multiplexer circuit; and

a BIST capture circuit.

5. The circuit of claim 4 , wherein the BIST multiplexer circuit includes a select input coupled to the preload port to select from at least one of the serial test data received at a first input port and memory pipeline output data received at a second input port.

6. The circuit of claim 1 , wherein the scan flops includes scan input latches coupled to receive outputs of the input latches included in the peripheral memory circuitry and having outputs configured to output scan test data to a bypass multiplexer circuit.

7. The circuit of claim 1 , wherein the embedded memory instance being an embedded Static Random Access Memory (SRAM).

8. The circuit of claim 1 , wherein the array of memory cells operate in functional mode without a refresh cycle.

9. The circuit of claim 1 , wherein timing associated with each of the functional data path, scan data path, and BIST data path is closed inside the embedded memory during a memory design phase.