IP Library Granted Patent US 8,625,348
Granted Patent B2
US 8,625,348 · App. 13/243,968 · Granted Jan 7, 2014

Nonvolatile memory devices and methods forming the same

Inventors: Changhyun Lee (Suwon-si, KR); Byoungkeun Son (Suwon-si, KR)
Assignee: Samsung Electronics Co., Ltd.
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Quick Facts
Patent No.
US 8,625,348
App. No.
13/243,968
Granted
Jan 7, 2014
Kind
B2
Abstract

Provided are nonvolatile memory devices and methods of forming the same. The nonvolatile memory device includes a plurality of word lines, a ground select line, string select line, and a dummy word line. Each of distances between the dummy word line and the ground select line and between the dummy word line and the word line is greater than a distance between a pair of the word lines adjacent to each other.

Claims (23)

1. A nonvolatile memory device comprising:

a plurality of word lines on a semiconductor substrate;

a ground select line at a side of the word lines;

a string select line at another side of the word lines;

a first dummy word line between the ground select line and a first word line, wherein the first word line is nearest to the ground select line among the word lines; and

a second dummy word line between the string select line and a second word line, wherein the second word line is nearest to the string select line among the word lines,

wherein each of a first distance between the ground select line and the first dummy word line and a second distance between the first dummy word line and the first word line is greater than a third distance between a pair of the word lines adjacent to each other.

2. The nonvolatile memory device of claim 1 , wherein each of a distance between the string select line and the second dummy word line and a distance between the second dummy word line and the second word line is greater than the third distance.

3. The nonvolatile memory device of claim 1 , wherein a channel region of the ground select line and a channel region of the first dummy word line have the same conductivity type as a conductivity type of the semiconductor substrate between the ground select line and the first dummy word line.

4. The nonvolatile memory device of claim 3 , wherein a source/drain region is induced in the semiconductor substrate between the channel regions of the ground select line and the first dummy word line by a fringe field.

5. The nonvolatile memory device of claim 1 , wherein a channel region of the string select line and a channel region of the second dummy word line have the same conductivity type as a conductivity type of the semiconductor substrate between the string select line and the second dummy word line.

6. The nonvolatile memory device of claim 1 , wherein channel regions of the word lines have the same conductivity type as a conductivity type of the semiconductor substrate between the channel regions of the word lines.

7. A nonvolatile memory device comprising:

gate patterns and insulating patterns alternately and repeatedly stacked on a semiconductor substrate;

semiconductor patterns penetrating the gate patterns and the insulating patterns and upwardly extending from the semiconductor substrate; and

a data storage layer disposed between the semiconductor patterns and the gate patterns,

wherein the gate patterns include a plurality of word lines, a ground select line under the word lines, a string select line on the word lines, a first dummy word line between the ground select line and a first word line, wherein the first word line is nearest to the ground select line among the word lines, and a second dummy word line between the string select line and a second word line, wherein the second word line is nearest to the string select line among the word lines, and

wherein each of a first distance between the ground select line and the first dummy word line and a second distance between the first dummy word line and the first word line is greater than a third distance between a pair of the word lines adjacent to each other.

8. The nonvolatile memory device of claim 7 , wherein a thickness of each of insulating patterns between the ground select line and the first dummy word line and between the first dummy word line and the first word line is greater than a thickness of each of insulating patterns between the word lines.

9. The nonvolatile memory device of claim 7 , wherein each of a distance between the string select line and the second dummy word line and a distance between the second dummy word line and the second word line is greater than the third distance.

10. The nonvolatile memory device of claim 9 , wherein a thickness of each of insulating patterns between the string select line and the second dummy word line and between the second dummy word line and the second line is greater than a thickness of each of the insulating patterns between the word lines.

11. The nonvolatile memory device of claim 7 , wherein the data storage layer includes a charge trapping layer having charge trap sites.

12. The nonvolatile memory device of claim 7 , wherein the data storage layer extends onto top surfaces and bottom surfaces of the gate patterns.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 23, 2011
From: LEE, CHANGHYUN; SON, BYOUNGKEUN
To: SAMSUNG ELECTRONICS CO., LTD
Reel/Frame 026966/0853 →
Priority Claims (1)
KR 10-2010-0096991 · Oct 5, 2010 · national
Continuity (1)
Related Publication 20120081958A1 · Apr 5, 2012