IP Library Granted Patent US 8,927,374
Granted Patent B2
US 8,927,374 · App. 13/252,346 · Granted Jan 6, 2015

Semiconductor device and fabrication method thereof

Inventors: Lilly Su (ChuBei, TW); Pang-Yen Tsai (Jhu-bei, TW); Tze-Liang Lee (Hsinchu, TW); Chii-Horng Li (Jhu-Bei, TW); Yen-Ru Lee (Hsinchu, TW); Ming-Hua Yu (Hsinchu, TW)
Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
H01L29/045H01L21/823412H01L21/823418H01L21/823425H01L21/823481H01L21/823807H01L21/823814H01L21/823878H01L29/66636H01L29/66659H01L29/7835H01L29/0843
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,927,374
App. No.
13/252,346
Granted
Jan 6, 2015
Kind
B2
Abstract

A method for fabricating a semiconductor device is disclosed. A strained material is formed in a cavity of a substrate and adjacent to an isolation structure in the substrate. The strained material has a corner above the surface of the substrate. The disclosed method provides an improved method for forming the strained material adjacent to the isolation structure with an increased portion in the cavity of the substrate to enhance carrier mobility and upgrade the device performance. The improved formation method is achieved by providing a treatment to redistribute at least a portion of the corner in the cavity.

Claims (41)

1. A method for fabricating a semiconductor device, comprising:

forming an isolation feature in a substrate;

forming a gate stack over the substrate;

forming a wedge-shaped recess cavity in the substrate, wherein the wedge-shaped recess cavity is horizontally positioned between the gate stack and the isolation feature;

forming an epitaxial (epi) material in the wedge-shaped recess cavity, wherein the epi material has a corner above the wedge-shaped recess cavity;

forming a cap layer over the epi material; and

providing a treatment to redistribute at least a portion of the corner to be in the wedge-shaped recess cavity, wherein a portion of the cap layer is within the cavity after the step of treatment.

2. The method of claim 1 , wherein the cap layer is formed before the step of treatment, and wherein a top surface of the epi material is inclined with respect to a top surface of the substrate.

3. The method of claim 2 , wherein the cap layer is Si formed by an epi growth process.

4. The method of claim 2 , wherein the cap layer is formed at a temperature lower than a temperature of the treatment.

5. The method of claim 2 , wherein the cap layer has a thickness not greater than about 5 nm.

6. The method of claim 1 , wherein the epi material is SiGe.

7. The method of claim 1 , wherein the epi material is formed at a temperature lower than a temperature of the treatment.

8. The method of claim 1 , further comprising:

forming a contact feature over the epi material after the treatment.

9. The method of claim 1 , wherein the epi material has a (311) crystal plane after the treatment.

10. The method of claim 1 , wherein the corner has a tip height ranging between about 1 nm and about 10 nm.

11. A method for fabricating a semiconductor device, comprising:

forming an isolation feature in a substrate;

forming a gate stack over the substrate;

forming a source/drain (S/D) wedge-shaped recess cavity in the substrate, wherein the S/D wedge-shaped recess cavity is positioned between the gate stack and the isolation feature;

forming an epitaxial (epi) material in the S/D wedge-shaped recess cavity, wherein the epi material has an upper surface with a crystal plane;

forming a cap layer over the S/D wedge-shaped recess cavity; and

heating the epi material to transform the upper surface to deviate from the crystal plane, wherein a portion of the cap layer is within the cavity after the step of heating.

12. The method of claim 11 , wherein the step of heating is performed at a temperature ranging between about 650° C. to about 850° C.

13. The method of claim 11 , further comprising:

forming an epi Si layer over the epi material at a temperature ranging between about 700° C. to about 800° C.

14. The method of claim 13 , further comprising:

forming a contact feature over the epi Si layer.

15. A method for fabricating a semiconductor device, comprising:

forming an isolation feature in a substrate;

forming a gate stack over the substrate;

forming a wedge-shaped recess cavity in the substrate, wherein the wedge-shaped recess cavity is horizontally positioned between the gate stack and the isolation feature;

forming an epitaxial (epi) material in the wedge-shaped recess cavity, wherein the epi material has a corner above the wedge-shaped recess cavity, and the epi material has an upper surface with a crystal plane;

forming a cap layer over the epi material; and

providing a treatment to redistribute at least a portion of the corner to be in the wedge-shaped recess cavity, wherein the treatment comprises heating the epi material, and heating the epi material transforms the upper surface to deviate from the crystal plane, wherein a portion of the cap layer is within the cavity after the step of treatment.

16. The method of claim 15 , wherein the treatment is performed at a temperature ranging from about 650° C. to about 850° C.

17. The method of claim 16 , wherein the treatment is performed under a pressure ranging from about 10 Torr to about 50 Torr for a duration not less than about 30 seconds.

18. The method of claim 15 , wherein forming the cap layer is performed at a temperature ranging from about 700° C. to about 800° C. in the presence of a silicon-containing gas.

19. The method of claim 18 , wherein forming the cap layer further comprises forming the cap layer in the presence of at least one of B 2 H 6 or H 2 .

20. The method of claim 18 , further comprising forming a contact feature over the cap layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2011
From: SU, LILLY; TSAI, PANG-YEN; LEE, TZE-LIANG; LI, CHII-HORNG; LEE, YEN-RU; YU, MING-HUA
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 027010/0953 →
Continuity (1)
Related Publication 20130082309A1 · Apr 4, 2013