Delegating network processor operations to star topology serial bus interfaces
View Patent ↗An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. The data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. In one aspect of an embodiment of the invention, the messaging network connects to a high-bandwidth star-topology serial bus such as a PCI express (PCIe) interface capable of supporting multiple high-bandwidth PCIe lanes. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.
1. A multi-core processor, comprising:
a plurality of processor cores; and
a messaging network disposed between the plurality of processor cores and a plurality of communication ports, the messaging network being configured to transfer packet data between the plurality of processor cores and the plurality of communication ports, wherein
to transfer the packet data, the messaging network is configured to:
receive, from a first communication port from among the plurality of communication ports, at least two packets of packet data for respective processing by at least two processor cores from among the plurality of processor cores,
transmit, to the at least two processor cores, the at least two packets of packet data for the respective processing,
receive, from the at least two processor cores, at least two processed packets of packet data, and
transmit the at least two processed packets of packet data to a second communication port from among the plurality of communication ports.
2. The multi-core processor of claim 1 , wherein the respective processing includes processing of the at least two packets of packet data by the at least two processor cores based on information included in headers of the at least two packets of packet data.
3. The multi-core processor of claim 1 , wherein the respective processing includes processing of the at least two packets of packet data by the at least two processor cores based on payload information included in the at least two packets of packet data.
4. The multi-core processor of claim 1 , wherein the messaging network is configured to receive the at least two packets of packet data in an order that is based on a current number of credits associated with each of the at least two processor cores.
5. The multi-core processor of claim 4 , wherein the current number of credits associated with each of the at least two processor cores is based on a processing speed of packet data by each of the at least two processor cores.
6. The multi-core processor of claim 4 , wherein the current number of credits associated with each of the at least two processor cores is based on a delay in processing of the packet data by each of the at least two processor cores.
7. The multi-core processor of claim 6 , wherein the messaging network is configured to transmit a packet, from among the at least two packets of packet data, to a processor core other than the at least two processor cores when a delay in processing of the packet data by a processor core, from among the at least two processor cores, is determined to be greater than a predetermined threshold.
8. The multi-core processor of claim 1 , wherein
each of the at least two packets of packet data is assigned a sequence number which is forwarded to the at least two processor cores and is included in the at least two processed packets of packet data to allow the at least two processed packets of packet data to be output from the multi-core processor based on the sequence number assigned to each of the at least two packets of packet data.
9. The multi-core processor of claim 1 , wherein each of the plurality of processor cores includes a data cache and an instruction cache, and the messaging network is disposed between the instruction cache of each of the plurality of processor cores and the plurality of communication ports.
10. The multi-core processor of claim 9 , farther comprising:
a data switch arrangement coupled to the data cache of each of the plurality of processor cores, the data switch arrangement being configured to transfer memory related information among the plurality of processor cores.
11. The multi-core processor of claim 1 , wherein
the messaging network is associated with a PCIe interface to a star-topology serial bus, the PCIe interface being coupled to an interconnect to receive memory requests from the plurality of processor cores, and comprising a direct memory access (DMA) engine to translate the memory requests into packets.
12. A method for processing packet data in a multi-core processor including a plurality of processor cores, the method comprising:
disposing a messaging network between the plurality of processor cores and a plurality of communication ports; and
transferring packet data between the plurality of processor cores and the plurality of communication ports, wherein the transferring comprises:
receiving, at the messaging network from a first communication port from among the plurality of communication ports, at least two packets of packet data for respective processing by at least two processor cores from among the plurality of processor cores,
transmitting, from the messaging network to the at least two processor cores, the at least two packets of packet data for the respective processing,
receiving, at the messaging network from the at least two processor cores, at least two processed packets of packet data, and
transmitting, from the messaging network to a second communication port from among the plurality of communication ports, the at least two processes packets of packet data.
13. The method of claim 12 , wherein the respective processing includes processing of the at least two packets of packet data by the at least two processor cores based on information included in headers of the at least two packets of packet data.
14. The method of claim 12 , wherein the respective processing includes processing of the at least two packets of packet data by the at least two processor cores based on payload information included in the at least two packets of packet data.
15. The method of claim 12 , wherein the receiving the at least two packets of packet data includes receiving the at least two packets of packet data in an order that is based on a current number of credits associated with each of the at least two processor cores.
16. The method of claim 15 , wherein the current number of credits associated with each of the at least two processor cores is based on a processing speed of packet data by each of the at least two processor cores.
17. The method of claim 15 , wherein the current number of credits associated with each of the at least two processor cores is based on a delay in processing of the packet data by each of the at least two processor cores.
18. The method of claim 17 , wherein the transmitting the at least two packets of packet data for respective processing includes transmitting a packet, from among the at least two packets of packet data, to a processor core other than the at least two processor cores when the delay in processing of the packet data by a processor core, from among the at least two processor cores, is determined to be greater than a predetermined threshold.
19. The method of claim 12 , further comprising:
assigning a sequence number to each of the at least two packets of packet data which is forwarded to the at least two processor cores and is included in the at least two processed packets of packet data, and
outputting the at least two processed packets of packet data from the multi-core processor based on the sequence number assigned to each of the at least two packets of packet data.
20. A multi-core processor, comprising:
a plurality of processor cores, each processor core including a data cache and an instruction cache;
a data switch arrangement coupled to the data cache of each of the plurality of processor cores, the data switch arrangement being configured to transfer information among the plurality of processor cores; and
a messaging network disposed between the instruction cache of each of the plurality of processor cores and a plurality of communication ports, the messaging network being configured to transfer, in parallel, packet data between the plurality of processor cores and the plurality of communication ports, wherein
to transfer the packet data, the messaging network is configured to:
receive, from a first communication port from among the plurality of communication ports, at least two packets of packet data for respective processing by at least two processor cores from among the plurality of processor cores,
transmit, to the at least two processor cores, the at least two packets of packet data for the respective processing,
receive, from the at least two processor cores, at least two processed packets of packet data, and
transmit the at least two processed packets of packet data to a second communication port from among the plurality of communication ports.
21. The multi-core processor of claim 20 , wherein
each of the at least two packets of packet data is assigned a sequence number which is forwarded to the at least two processor cores and is included in the at least two processed packets of packet data to allow the at least two processed packets of packet data to be output from the multi-core processor based on the sequence number assigned to each of the at least two packets of packet data.