Leadless array plastic package with various IC packaging configurations

1. A method of manufacturing a leadless integrated circuit (IC) package comprising:

providing a leadframe strip having top and bottom surfaces;

removing portions of the top surface of the leadframe strip to form recesses therein partially defining upper portions of one or more die-attach areas and upper portions of a plurality of electrical contacts;

mounting a first IC chip to the leadframe strip in a first die-attach area of the partially defined one or more die-attach areas;

mounting a second IC chip in a second die-attach area of the partially defined one or more die-attach areas;

forming electrical connections between the plurality of partially defined electrical contacts and the first IC chip;

covering the first IC chip, the second IC chip, the partially defined one or more die-attach areas, the partially defined electrical contacts, and the electrical connections with a molding layer, the molding layer filling the recesses;

forming an etch-resist layer on the bottom surface of the leadframe strip corresponding to the partially defined one or more die-attach areas and the plurality of partially defined electrical contacts; and

selectively etching the bottom surface of the leadframe strip using the etch-resist layer as an etching mask, thereby etching through portions of the leadframe strip to define lower portions of the plurality of electrical contacts and lower portions of the one or more die-attach areas.

2. The method of claim 1 , wherein the second IC chip is mounted to the first IC chip in a stacked configuration.

3. The method of claim 1 , wherein the second IC chip is mounted to the leadframe strip in a generally side-by-side configuration relative to the first IC chip.

4. The method of claim 3 , wherein the first die-attach area is contiguous with the second die-attach area.

5. The method of claim 2 , wherein the first die-attach area comprises a plurality of flip-chip terminals and the first IC chip is mounted thereto in a flip-chip configuration.

6. The method of claim 3 , wherein the first die-attach area comprises a plurality of flip-chip terminals and the first IC chip is mounted thereto in a flip-chip configuration.

7. The method of claim 1 and further comprising:

mounting an electronic component to the leadframe strip.

8. The method of claim 7 , wherein the electronic component is selected from the group comprising: a resistor, a capacitor, and an inductor.

9. The method of claim 1 and further comprising:

wirebonding the first IC chip to first and second electrical contacts of the plurality of electrical contacts; and

wirebonding the first and second contacts together with one or more electrical contacts of the plurality of electrical contacts in a daisy-chain configuration to provide inductance to the first IC chip.

10. The method of claim 2 , wherein the first IC chip and the second IC chip are separated by a non-conductive spacer material disposed therebetween.

11. The method of claim 2 and further comprising:

electrically coupling the second IC chip to the first IC chip via a plurality of wirebonds.

12. The method of claim 2 and further comprising:

wirebonding the second IC chip to at least one electrical contact of the plurality of electrical contacts.

13. The method of claim 2 , wherein the electrical connections are wirebonds.

14. The method of claim 5 and further comprising:

wirebonding the second IC chip to at least one electrical contact of the plurality of electrical contacts.

15. The method of claim 5 and further comprising:

electrically coupling the second IC chip to the first IC chip via one or more wirebonds between the second IC chip and one or more flip-chip terminals of the plurality of flip-chip terminals.

16. The method of claim 3 and further comprising:

electrically coupling the first IC chip and the second IC chip to the plurality of electrical contacts via wirebonds.

17. The method of claim 16 and further comprising:

electrically coupling the first IC chip to the second IC chip via wirebonds.

18. The method of claim 3 , and further comprising:

a memory chip mounted to the first IC chip in a stacked configuration.

19. A method of manufacturing a leadless integrated circuit (IC) package comprising:

providing a leadframe strip having top and bottom surfaces;

removing portions of the top surface of the leadframe strip to form recesses therein partially defining an upper portion of a die-attach area and an upper portion of a plurality of electrical contacts;

mounting an IC chip assembly to the leadframe strip in the partially defined die-attach area, the IC chip assembly comprising a first die and a second die mounted on a top surface thereof in a stacked configuration;

forming electrical connections between the plurality of partially defined electrical contacts and the IC chip assembly;

covering the IC chip assembly, the partially defined die-attach area, the partially defined electrical contacts, and the electrical connections with a molding layer, the molding layer filling the recesses;

forming an etch-resist layer on the bottom surface of the leadframe strip corresponding to the partially defined die-attach area and the plurality of partially defined electrical contacts; and

selectively etching the bottom surface of the leadframe strip using the etch-resist layer as an etching mask, thereby etching through portions of the leadframe strip to define lower portions of the plurality of electrical contacts and a lower portion of the die-attach area.

20. The method of claim 19 , wherein the die-attach area comprises a die-attach pad.

21. The method of claim 19 , wherein the die-attach area comprises a plurality of flip-chip terminals and the first die is mounted thereon in a flip-chip configuration.

22. A method of manufacturing a leadless integrated circuit (IC) package comprising:

providing a leadframe strip having top and bottom surfaces;

removing portions of the top surface of the leadframe strip to form recesses therein partially defining upper portions of first and second die-attach areas and upper portions of a plurality of electrical contacts;

mounting a first IC chip to the leadframe strip in the first partially defined die-attach area;

mounting a second IC chip to the leadframe strip in the second partially defined die-attach area;

forming electrical connections between the electrical contacts and the first and second IC chips;

covering the first and second IC chips, the first and second partially defined die-attach areas, the plurality of partially defined electrical contacts, and the electrical connections with a molding layer, the molding layer filling the recesses;

forming an etch-resist layer on the bottom surface of the leadframe strip corresponding to the first and second partially defined die-attach areas and the plurality of partially defined electrical contacts; and

selectively etching the bottom surface of the leadframe strip using the etch-resist layer as an etching mask, thereby etching through portions of the leadframe strip to define lower portions of the plurality of electrical contacts and the first and second die-attach areas.

23. The method of claim 22 , wherein the first die-attach area is a die-attach pad.

24. The method of claim 22 , wherein the second die-attach area is a die-attach pad.

25. The method of claim 22 , wherein the first die-attach area comprises a plurality of flip-chip terminals and the first IC chip is mounted thereon in a flip-chip configuration.

26. The method of claim 22 , wherein the second die-attach area comprises a plurality of flip-chip terminals and the second IC chip is mounted thereon in a flip-chip configuration.

27. A method of manufacturing a leadless integrated circuit (IC) package comprising:

providing a leadframe strip having top and bottom surfaces;

removing portions of the top surface of the leadframe strip to form recesses therein partially defining upper portions of a plurality of electrical contacts;

mounting an IC chip to the plurality of partially defined electrical contacts in a flip-chip configuration;

forming electrical connections between the plurality of partially defined electrical contacts and the IC chip;

covering the IC chip and the plurality of partially defined electrical contacts with a molding layer, the molding layer filling the recesses;

forming an etch-resist layer on the bottom surface of the leadframe strip corresponding to the plurality of partially defined electrical contacts; and

selectively etching the bottom surface of the leadframe strip using the etch-resist layer as an etching mask, thereby etching through portions of the leadframe strip to define lower portions of the plurality of electrical contacts.

28. A method of manufacturing a leadless integrated circuit (IC) package comprising:

providing a leadframe strip having top and bottom surfaces;

removing portions of the top surface of the leadframe strip to form recesses therein partially defining an upper portion of a die-attach area and an upper portion of a plurality of electrical contacts;

forming sidewalls around a periphery of the leadframe strip;

filling the recesses with a molding layer;

mounting an IC chip to the leadframe strip in the partially defined die-attach area;

forming electrical connections between the plurality of partially defined electrical contacts and the IC chip;

providing a lid configured to be attached to the sidewalls;

attaching the lid to the sidewalls, the lid, the sidewalls, the leadframe strip, and the molding layer defining a sealed air cavity therein;

forming an etch-resist layer on the bottom surface of the leadframe strip corresponding to the partially defined die-attach area and the plurality of partially defined electrical contacts; and

selectively etching the bottom surface of the leadframe strip using the etch-resist layer as an etching mask, thereby defining the plurality of electrical contacts and the die-attach area as separate component.

29. The method of claim 28 , wherein the lid is opaque.

30. The method of claim 28 , wherein the lid comprises an optical quality glass lens.

31. A method of manufacturing a leadless integrated circuit (IC) package comprising:

providing a leadframe strip having top and bottom surfaces;

removing portions of the top surface of the leadframe strip to form recesses therein partially defining an upper portion of a die-attach area and upper portions of a plurality of electrical contacts;

mounting an IC chip to the leadframe strip in the partially patterned die-attach area;

mounting a passive electronic component to the plurality of partially patterned electrical contacts;

forming electrical connections between the plurality of partially defined electrical contacts and the IC chip;

covering the IC chip, the passive electronic component, the partially defined at least one die-attach area, the partially defined electrical contacts, and the electrical connections with a molding layer, the molding layer filling the recesses;

forming an etch-resist layer on the bottom surface of the leadframe strip corresponding to the partially defined at least one die-attach area and the plurality of partially defined electrical contacts; and

selectively etching the bottom surface of the leadframe strip using the etch-resist layer as an etching mask, thereby etching through portions of the leadframe strip to define lower portions of the plurality of electrical contacts and a lower portion of the at least one die-attach area.

32. The method of claim 31 , wherein the passive electronic component is selected from the group comprising: a resistor, a capacitor, and an inductor.