Active pin connection monitoring system and method
A system for monitoring a connection to an active pin of an integrated circuit (IC) die, includes an input/output (I/O) cell of an IC die, where the I/O cell is bonded to a bonding pad on a ball grid array (BGA) substrate. The system includes a test point on a printed circuit board (PCB) coupled to the bonding pad which forms an electrical/conductive pathway between the test point and the I/O cell. The system includes a clock waveform injected through a resistor into the test point.
1. A method of monitoring a connection to an active pin of an integrated circuit (IC) die comprising:
injecting a first waveform through a resistor onto a conductive path associated with an input/output (I/O) cell of an active pin of an IC die, wherein the first waveform is injected at a first pin of the resistor and a second pin of the resistor is coupled to the conductive path;
monitoring the first waveform at the first pin and a second waveform at the second pin;
comparing the first waveform at the first pin with the second waveform at the second pin; and
determining that there is a break in the conductive path when the second waveform at the second pin is substantially the same as the first waveform at the first pin.
2. A method as recited in claim 1 , further comprising determining that there is not a break in the conductive path when the second waveform at the second pin is degraded from the first waveform at the first pin.
3. A method as recited in claim 2 , wherein determining that there is not a break in the conductive path comprises determining that the second waveform at the second pin substantially matches a predetermined waveform simulated according to known electrical characteristics of the I/O cell.
4. A method as recited in claim 1 , wherein the injecting a first waveform comprises injecting a clock signal having a frequency of 100 megahertz and an amplitude of 5 volts.
5. A method as recited in claim 1 , wherein the IC die is wire-bonded to a ball grid array (BGA) substrate and the active pin is coupled to the conductive path through a solder joint located at a corner of the BGA substrate between the BGA substrate and a printed circuit board.
6. A method as recited in claim 1 , wherein the IC die is flip-chip-bonded to a ball grid array (BGA) substrate and the active pin is coupled to the conductive path through a solder joint located at a corner of the BGA between the BGA and a printed circuit board.
7. A method of monitoring a connection to an active pin of an integrated circuit (IC) die comprising:
injecting a first waveform through a resistor onto a conductive path associated with an input/output (I/O) cell of an active pin of an IC die, wherein the first waveform is injected at a first pin of the resistor and a second pin of the resistor is coupled to the conductive path;
monitoring a second waveform at the second pin of the resistor;
comparing the second waveform at the second pin to a predetermined waveform simulated according to known electrical characteristics of the I/O cell; and
determining that there is a break in the conductive path when the second waveform at the second pin is not substantially the same as the predetermined waveform.
8. A method as recited in claim 7 , wherein the predetermined waveform is a simulated waveform based on known electrical characteristics of the I/O cell, a known value of the resistor, and characteristics of the first waveform.
9. A method as recited in claim 7 , further comprising determining that there is not a break in the conductive path when the second waveform at the second pin is substantially the same as the predetermined waveform.
10. A method as recited in claim 7 , wherein the predetermined waveform represents a degraded version of the first waveform injected at the first pin.
11. A method as recited in claim 7 , further comprising simulating the predetermined waveform based on known electrical characteristics of the I/O cell, a known value of the resistor, and characteristics of the first waveform.
12. A system for monitoring a connection to an active pin of an integrated circuit (IC) die, comprising:
an input/output (I/O) cell of an IC die, the I/O cell bonded to a bonding pad on a ball grid array (BGA) substrate;
a test point on a printed circuit board (PCB) coupled to the bonding pad and forming an electrical connection pathway between the test point and the I/O cell; and
a first waveform injected through a resistor into the test point,
wherein a break in the electrical connection pathway is determined when a second waveform at the test point is substantially the same as the first waveform.
13. The system of claim 12 , wherein the bond between the I/O cell and the bonding pad is a wire bond.
14. The system of claim 12 , wherein the IC die is flip-chip bonded to the BGA substrate and the bond between the I/O cell and the bonding pad is a solder joint.
15. The system of claim 12 , wherein the resistor is approximately 1 kilo-ohm and the first waveform comprises a clock waveform having a frequency of approximately 100 megahertz.
16. The system of claim 12 , wherein no break in the electrical connection pathway is determined when the second waveform at the test point is degraded from the first waveform.
17. The system of claim 12 , wherein no break in the electrical connection pathway is determined when the second waveform at the test point substantially matches a predetermined waveform simulated according to known electrical characteristics of the I/O cell.