Granted Patent B2

US 9,590,027 · App. 13/264,816 · Granted Mar 7, 2017

Abstract

Claims (32)

1. A method for fabricating an electronic component, the method comprising:

fabricating, on a substrate, at least one integrated MIM capacitor having a top capacitor electrode, and a bottom capacitor electrode at a smaller distance from the substrate than the top capacitor electrode;

fabricating an electrically insulating first cover layer on the top capacitor electrode, wherein the first cover layer at least partly covers the top capacitor electrode and includes a lead-containing dielectric material;

thinning the first cover layer, wherein the thinning step removes a more than proportional amount of lead from the lead-containing dielectric material such that the lead-containing dielectric material has a lower concentration of lead after the thinning step than before the thinning step;

fabricating an electrically insulating second cover layer on the first cover layer, wherein the second cover layer at least partly covers the first cover layer and has a dielectric permittivity smaller than that of the first cover layer; and

fabricating an electrically conductive resistor layer on the second cover layer, wherein the resistor layer has a defined ohmic resistance.

2. The method of claim 1 , wherein thinning the first cover layer comprises:

sputtering the first cover layer back.

3. The method of claim 1 , wherein thinning the first cover layer comprises:

etching the first cover layer back.

4. The method of claim 1 , wherein thinning the first cover layer comprises:

removing between 10 and 50 nanometers of the first cover layer.

5. The method of claim 1 , wherein the first cover layer includes lead zirconate titanate (PZT).

6. The method of claim 1 , wherein the first cover layer has a thickness of between 30 and 300 nm after the thinning step.

7. The method of claim 1 , wherein the resistor layer is made of at least one element from a group of Mo, Ni, Cr, Ti, Si, and W.

8. The method of claim 1 , wherein fabricating the MIM capacitor comprises:

fabricating a dielectric layer of the MIM capacitor, wherein the dielectric layer has a relative dielectric permittivity of between 100 and 5000.

9. The method of claim 1 , wherein the second cover layer is made of silicon nitride.

10. The method of claim 1 , further comprising:

fabricating a bottom barrier layer of a dielectric material between the substrate and the bottom capacitor electrode.

11. The method of claim 1 , further comprising:

fabricating a direct connection of the resistor layer with the top capacitor electrode.

12. The method of claim 1 , further comprising:

fabricating at least one active semiconductor element on an identical substrate.

13. The method of claim 12 , wherein the at least one active semiconductor element is an ESD protection diode.

14. The method of claim 1 , wherein a top portion of the first cover layer has a lower concentration of lead after the thinning step than before the thinning step.

15. The method of claim 1 , wherein the second cover layer is fabricated with a higher thickness than the first cover layer.

16. The method of claim 1 , wherein an interconnect layer is deposited directly upon the resistor layer.

17. The method of claim 1 , wherein the resistor layer is fabricated to form an inductor with an inductance of a desired value.

18. The method of claim 1 , wherein the second cover layer is made of silicon oxynitride.

19. The method of claim 1 , wherein the second cover layer is made of spin-on-glass (SOG).

20. The method of claim 10 , wherein the bottom barrier layer includes lead zirconate titanate (PZT).

Assignments (12)