Heterogeneous multi-core integrated circuit and method for debugging same
View Patent ↗A heterogeneous multi-core integrated circuit includes first and second sets of processor cores and corresponding first and second test access ports (TAPs). The first and second TAPs are connected to corresponding first and second debug ports by way of corresponding first and second TAP controllers. A debug control circuit is connected between the first and second TAP controllers and the first and second debug ports. Based on external configuration signals, the debug control circuit configures the connections between the first and second TAP controllers and the first and second debug ports according to predetermined configuration modes, which allows flexibility in debugging the heterogeneous multi-core integrated circuit.
1. A multi-core integrated circuit, comprising:
a plurality of processor cores including a first set of processor cores and a second set of processor cores, wherein the first and second sets of processor cores include corresponding first and second sets of test access ports (TAPs);
a plurality of TAP controllers corresponding to the plurality of processor cores, wherein the plurality of TAP controllers includes first and second TAP controllers connected to the first and second sets of processor cores respectively, and wherein the first and second TAP controllers connect the corresponding first and second sets of TAPs to corresponding first and second debug ports of the multi-core integrated circuit; and
a debug control circuit connected between the plurality of TAP controllers and the first and second debug ports, wherein the debug control circuit includes at least one mode select pin for receiving a configuration signal from an external debugging apparatus and generating at least one select signal, wherein the debug control circuit configures the first and second TAP controllers and the corresponding first and second debug ports in a predetermined debugging mode, based on the at least one select signal, and receives input data at at least one of the first debug port and the second debug port from the external debugging apparatus, and routes output debug data to at least one of the first and second debug ports, based on debugging of at least one of the first and second sets of processor cores by the external debugging apparatus.
2. The multi-core integrated circuit of claim 1 , wherein the first and second debug ports each comprise a test data in (TDI) interface, a test data out (TDO) interface, a test clock (TCK) interface, a test mode select (TMK) interface and an optional test reset (TRST) interface.
3. The multi-core integrated circuit of claim 1 , wherein the predetermined debugging mode comprises connecting the first and second TAP controllers in a daisy chain mode for debugging the first and the second sets of processor cores concurrently through the first debug port.
4. The multi-core integrated circuit of claim 1 , wherein the predetermined debugging mode comprises connecting the first debug port to the second TAP controller for debugging the second set of processor cores through the first debug port.
5. The multi-core integrated circuit of claim 1 , wherein the predetermined debugging mode comprises connecting the first debug port to the first TAP controller for performing at least one of a boundary scan of the multi-core integrated circuit and debugging of the first set of processor cores.
6. The multi-core integrated circuit of claim 1 , wherein the predetermined debugging mode comprises connecting the second debug port to the second TAP controller for debugging the second set of processor cores.
7. The multi-core integrated circuit of claim 1 , wherein the debug control circuit receives the input data at each of the first and second debug ports.
8. The multi-core integrated circuit of claim 7 , wherein the predetermined debugging mode comprises connecting the first and second debug ports to the respective first and second TAP controllers for debugging the respective first and second sets of processor cores concurrently.
9. The multi-core integrated circuit of claim 1 , wherein the debug control circuit includes a set of multiplexers connected between the at least one select pin, the first and second debug ports and the first and second TAP controllers, for configuring the connections between the first and second debug ports and the respective first and second TAP controllers, based on at least one of the predetermined debugging mode and the at least one select signal.
10. The multi-core integrated circuit of claim 1 , wherein each of the first and second TAP controllers include a set of data and instruction registers for storing and processing functions associated with the first and second TAP controllers.
11. The multi-core integrated circuit of claim 1 , wherein the multi-core integrated circuit is a heterogeneous multi-core integrated circuit.
12. The multi-core integrated circuit of claim 1 , wherein the first set of processor cores are general purpose processors.
13. The multi-core integrated circuit of claim 1 , wherein the second set of processor cores are digital signal processors (DSPs).
14. A method for debugging an multi-core integrated circuit, wherein the multi-core integrated circuit includes a plurality of processor cores including a first set of processor cores and a second set of processor cores, and wherein respective test access ports (TAPs) of the first and second sets of processor cores are connected to first and second debug ports of the multi-core integrated circuit by way of corresponding first and second TAP controllers respectively, and wherein the multi-core integrated circuit further includes a debug control circuit connected between the first and second TAP controllers and the corresponding first and second debug ports, the method comprising:
receiving a configuration signal at at least one mode select pin of the debug control circuit, from an external debugging apparatus;
generating at least one select signal by the at least one mode select pin, based on the configuration signal;
configuring the first and second TAP controllers and the corresponding first and second debug ports in a predetermined debugging mode, based on the at least one select signal;
receiving input data at at least one of the first debug port and the second debug port from the external debugging apparatus;
debugging at least one of the first and second sets of processor cores by the external debugging apparatus, based on the predetermined debugging mode; and
routing output debug data to at least one of the first and second debug ports.
15. The method of claim 14 , wherein the predetermined debugging mode comprises connecting the first and second TAP controllers in a daisy chain mode for debugging the first and the second sets of processor cores concurrently through the first debug port.
16. The method of claim 14 , wherein the predetermined debugging mode comprises connecting the first debug port to the second TAP controller for debugging the second set of processor cores through the first debug port.
17. The method of claim 14 , wherein the predetermined debugging mode comprises connecting the first debug port to the first TAP controller for performing at least one of a boundary scan of the multi-core integrated circuit and debugging of the first set of processor cores.
18. The method of claim 14 , wherein the predetermined debugging mode comprises connecting the second debug port to the second TAP controller for debugging the second set of processor cores.
19. The method of claim 14 , further comprising receiving the input data at each of the first and second debug ports.
20. The method of claim 19 , wherein the predetermined debugging mode comprises connecting the first and second debug ports to the respective first and second TAP controllers for debugging the first and second sets of processor cores concurrently.