METHODS OF FABRICATING FIELD EFFECT TRANSISTORS INCLUDING TITANIUM NITRIDE GATES OVER PARTIALLY NITRIDED OXIDE AND DEVICES SO FABRICATED
A gate of an integrated circuit field effect transistor is fabricated by fabricating a gate insulating layer on an integrated circuit substrate, fabricating a metal nitride layer on the gate insulating layer, annealing the metal nitride layer in a nitridizing ambient and fabricating a cap on the metal nitride layer that has been annealed. Thereafter, the cap on the metal nitride layer may be etched to expose sidewalls thereof and another anneal in a nitridizing ambient may take place. Related integrated circuit field effect transistors are also described.
1 . A method of fabricating an integrated circuit field effect transistor gate, the method comprising:
fabricating a gate insulating layer on an integrated circuit substrate;
fabricating a metal nitride layer on the gate insulating layer;
annealing the metal nitride layer in a nitridizing ambient; and
fabricating a cap on the metal nitride layer that has been annealed in the nitridizing ambient.
2 . A method according to claim 1 , wherein the nitridizing ambient comprises a first nitridizing ambient, the method further comprising:
etching the cap and the metal nitride layer that has been annealed in the first nitridizing ambient to expose sidewalls thereof; and
annealing a sidewall of the metal nitride layer in a second nitridizing ambient.
3 . A method according to claim 1 wherein annealing the metal nitride layer in a nitridizing ambient comprises annealing the metal nitride layer in an ambient that comprises NH 3 .
4 . A method according to claim 3 wherein annealing the metal nitride layer in an ambient that comprises NH 3 is performed at about 700° C. and about 30 Torr for about 60 seconds.
5 . A method according to claim 1 wherein annealing the metal nitride layer in a nitridizing ambient comprises annealing the metal nitride layer in an ambient that comprises N 2 O, NO, N 2 and/or CN at between about 500° C. and about 900° C., between about 760 Torr and about 1 Torr for between about 5 sec and about 400 sec.
6 . A method according to claim 2 wherein annealing the sidewall of the metal nitride layer in a second nitridizing ambient comprises annealing the sidewall of the metal nitride layer in an ambient that comprises N 2 O, NH 3 and He.
7 . A method according to claim 6 wherein annealing the sidewall of the metal nitride layer in an ambient that comprises N 2 O, NH 3 and He comprises annealing the sidewall of the metal nitride layer in an ambient that comprises N 2 O, NH 3 and He at respective flow rates of 50/300/1615 seem, at about 400° C. and about 7 Torr for about 30 seconds, at an applied RF power of about 100 W.
8 . A method according to claim 2 wherein annealing the sidewall of the metal nitride layer in a second nitridizing ambient comprises annealing the sidewall of the metal nitride layer in an ambient that comprises N 2 and/or CN at between about 200° C. and about 500° C., between about 1 Torr and about 760 Torr for between about 10 sec and about 400 sec at an applied RF power of about 5 kW.
9 . A method according to claim 2 wherein the first and second nitridizing ambients include at least one common constituent.
10 . A method according to claim 1 wherein the gate insulating layer comprises silicon dioxide and/or partially nitrided oxide, wherein the metal nitride layer comprises TiN and wherein the cap comprises polysilicon.
11 . An integrated circuit field effect transistor that is fabricated according to the method of claim 1 .
12 . An integrated circuit field effect transistor that is fabricated according to the method of claim 2 .
13 . A method of fabricating an integrated circuit field effect transistor gate, the method comprising:
fabricating a gate insulating layer on an integrated circuit substrate;
fabricating a metal nitride layer on the gate insulating layer;
fabricating a cap on the metal nitride layer;
etching the cap and the metal nitride layer to expose sidewalls thereof; and
annealing a sidewall of the metal nitride layer in a nitridizing ambient.
14 . A method according to claim 13 wherein annealing the sidewall of the metal nitride layer in a nitridizing ambient comprises annealing the sidewall of the metal nitride layer in an ambient that comprises N 2 O, NH3 and He.
15 . A method according to claim 14 wherein annealing the sidewall of the metal nitride layer in an ambient that comprises N 2 O, NH 3 and He comprises annealing the sidewall of the metal nitride layer in an ambient that comprises N 2 O, NH 3 and He at respective flow rates of 50/300/1615 seem, at about 400° C. and about 7 Torr for about 30 seconds, at an applied RF power of about 100 W.
16 . A method according to claim 13 wherein annealing the sidewall of the metal nitride layer in a nitridizing ambient comprises annealing the sidewall of the metal nitride layer in an ambient that comprises N 2 and/or CN at between about 200° C. and about 500° C., between about 1 Torr and about 760 Torr for between about 10 sec and about 400 sec at an applied RF power of about 5 kW.
17 . A method according to claim 13 wherein the gate insulating layer comprises silicon dioxide and/or partially nitrided oxide, wherein the metal nitride layer comprises TiN and wherein the cap comprises polysilicon.
18 . An integrated circuit field effect transistor that is fabricated according to the method of claim 13 .
19 . A method of fabricating an integrated circuit field effect transistor gate, the method comprising:
fabricating a gate insulating layer on an integrated circuit substrate;
fabricating a metal nitride layer on the gate insulating layer;
reducing interaction between the gate insulating layer and the metal nitride layer; and
fabricating a cap on the metal nitride layer after interaction between the gate insulating layer and the metal nitride layer has been reduced.
20 . A method according to claim 19 , further comprising:
etching the cap and the metal nitride layer to expose sidewalls thereof; and
converting at least some metal at the exposed sidewall of the metal nitride layer back to the metal nitride.