Bridge circuit providing a polarity insensitive power connection
In one general aspect, an apparatus can include a polarity insensitive input coupled to a gate of a metal-oxide-semiconductor field effect transistor (MOSFET) device. The MOSFET device can have a gate dielectric rating greater than twenty-five volts. The apparatus can also include a fixed polarity output coupled to a source of the MOSFET device.
1. An apparatus, comprising:
an n-channel metal-oxide-semiconductor field effect transistor (MOSFET) device, the n-channel MOSFET device being a vertical MOSFET device having a drain on a bottom portion of the n-channel MOSFET device and having a source pad on a top portion of the n-channel MOSFET device;
a p-channel MOSFET device having a drain on a bottom portion of the p-channel MOSFET device and having a source pad on a top portion of the p-channel MOSFET device;
a first lead frame portion defining a first polarity insensitive input, the drain of the n-channel MOSFET device and the drain of the p-channel MOSFET device both being disposed on the first lead frame portion;
a voltage limiter circuit disposed on top of the source pad of the n-channel MOSFET between the source pad and a gate pad of the n-channel MOSFET device, the voltage limiter circuit including a zener diode and a polysilicon resistor;
a second lead frame portion defining a second polarity insensitive input coupled to the gate bad of the n-channel MOSFET device via a first wire interconnect,
the zener diode, the polysilicon resistor and the n-channel MOSFET all being electrically connected to the second polarity insensitive input via the first wire interconnect and via the gate pad of the n-channel MOSFET device, the n-channel MOSFET device having a gate dielectric rating greater than twenty-five volts; and
a third lead frame portion defining a fixed polarity output coupled to the source pad of the n-channel MOSFET device via a second wire interconnect.
2. The apparatus of claim 1 , wherein the n-channel MOSFET device has a gate voltage rating approximately equal to a drain-to-source voltage rating of the n-channel MOSFET device.
3. The apparatus of claim 1 , wherein the n-channel MOSFET device is a first n-channel MOSFET device,
the apparatus further comprising:
a second n-channel MOSFET device having a source pad coupled to the fixed polarity output and a gate bad coupled to the first polarity insensitive input, the second n-channel MOSFET device being disposed on the second lead frame portion defining the second polarity insensitive input.
4. The apparatus of claim 1 , wherein
the fixed polarity output is a first fixed polarity output, the source pad of the p-channel MOSFET device being coupled to a second fixed polarity output.
5. The apparatus of claim 1 , wherein the gate dielectric has a thickness greater than 50 nanometers.
6. The apparatus of claim 1 , wherein the first polarity insensitive input functions as an input for a power over Ethernet connection.
7. The apparatus of claim 1 , wherein
the zener diode and the resistor are collectively configured to limit current through the voltage limiter circuit.
8. The apparatus of claim 1 , wherein the drain of the n-channel MOSFET device, the source pad of the n-channel MOSFET device, and the voltage limiter are vertically disposed between the first lead frame portion and the gate pad.
9. The apparatus of claim 1 , wherein the voltage limiter circuit consists of the zener diode and the polysilicon resistor.
10. The apparatus of claim 1 , wherein the voltage limiter circuit is integrated into the n-channel MOSFET device.
11. An apparatus, comprising:
a lead frame including:
a fixed positive output terminal,
a fixed negative output terminal,
a first polarity insensitive input terminal, and
a second polarity insensitive input terminal;
a p-channel MOSFET device including a source pad on a top portion of the p-channel MOSFET device and coupled to the fixed positive output terminal, the p-channel MOSFET device having a drain, the p-channel MOSFET device having a gate pad coupled to the second polarity insensitive input terminal; and
an n-channel MOSFET device including a source pad coupled to the fixed negative output terminal via a first interconnect, the n-channel MOSFET device having a drain, the n-channel MOSFET device having a gate pad coupled to the second polarity insensitive input terminal via a second interconnect, the n-channel MOSFET device being a vertically-oriented MOSFET device,
the drain of the n-channel MOSFET device and the drain of the p-channel MOSFET device both being disposed on top of the first polarity insensitive input terminal; and
a voltage limiter circuit disposed on top of the source pad of the n-channel MOSFET between the source pad and the gate pad of the n-channel MOSFET device, the voltage limiter circuit including a zener diode and a polysilicon resistor.
12. The apparatus of claim 11 , wherein the lead frame, the p-channel MOSFET device, and the n-channel MOSFET device are packaged as a single, discrete component.
13. The apparatus of claim 11 , wherein at least one of the p-channel MOSFET device or the n-channel MOSFET device have a gate dielectric rating greater than twenty-five volts, and a voltage rating of the gate pad of the n-channel MOSFET device is approximately equal to a drain-to-source voltage rating of the n-channel MOSFET device.
14. The apparatus of claim 11 , wherein the drain of the n-channel MOSFET device is directly coupled to the first polarity insensitive input terminal without an intervening component.
15. The apparatus of claim 11 , wherein the n-channel MOSFET device includes a gate dielectric having a thickness greater than 50 nanometers.
16. An apparatus, comprising:
a four-terminal lead frame including a pair of polarity insensitive input terminals and a pair of output terminals;
a first p-channel MOSFET device and a first n-channel MOSFET device disposed on a first polarity insensitive input terminal from the pair of polarity insensitive input terminals, the first p-channel MOSFET device being operably coupled to a first output terminal from the pair of output terminals of the four terminal lead frame via a first wire interconnect; and
a second p-channel MOSFET device and a second n-channel MOSFET device disposed on a second polarity insensitive input terminal from the pair of polarity insensitive input terminals, the second p-channel MOSFET device being operably coupled to the first output terminal from the pair of output terminals of the four terminal lead frame via a second wire interconnect,
a voltage limiter circuit disposed on top of a source pad of the first n-channel MOSFET between the source pad and a gate pad of the first n-channel MOSFET device, the voltage limiter circuit including a zener diode and a polysilicon resistor.
17. The apparatus of claim 16 , wherein the first p-channel MOSFET device is a vertically-oriented MOSFET device having a drain coupled on the first polarity insensitive input terminal, and
the first n-channel MOSFET device is a vertically-oriented MOSFET device having a drain coupled to the first polarity insensitive input terminal.
18. The apparatus of claim 16 , further comprising:
a third wire interconnect operably coupling a gate of the first n-channel MOSFET device and the voltage limiter circuit to the second polarity insensitive input terminal of the four-terminal lead frame.
19. The apparatus of claim 16 , wherein at least one of the first p-channel MOSFET device or the first n-channel MOSFET device has a gate dielectric rating greater than twenty-five volts.
20. The apparatus of claim 16 , wherein the voltage limiter circuit is configured to limit current, the zener diode is configured to function as a clamping diode.