IP Library Patent Application 13272725
Patent Application
App. No. 13/272,725

MULTIPLE CORE DATA PROCESSOR WITH USAGE MONITORING

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Quick Facts
Patent No.
US None
App. No.
13/272,725
Abstract

A data processor with a plurality of processor cores. Accumulated usage information of each of the plurality of processor cores is stored in a storage device within the data processor, wherein the accumulated usage information is indicative of accumulated usage of each processor core of the plurality of processor cores. The processor uses the accumulated usage information in selecting processor cores to perform processor operations.

Claims (50)

1 . In a multi core data processor, a method comprising:

receiving an indication to perform a processor operation;

selecting at least one selected processor core of a plurality of processor cores of the data processor to perform the processor operation, wherein the selecting includes using accumulated usage information of at least one of the plurality of processor cores, wherein accumulated usage information of a processor core is indicative of accumulated usage of the processor core; and

performing the processor operation by the at least one selected processor core.

2 . The method of claim 1 further comprising:

wherein the selecting includes not selecting cores having an allocated usage that exceeds a lifetime maximum allocated usage of the core.

3 . The method of claim 1 further comprising:

when a lifetime maximum allocated usage is determined to have been exceeded by a core of the at least one selected processor core, modifying the operation of the data processor to change an operating condition parameter of the at least one selected processor core.

4 . The method of claim 1 further comprising retrieving accumulated usage information of the plurality of processor cores including the at least one selected processor core and using the accumulated usage information retrieved in the selecting.

5 . The method of claim 1 wherein:

the selecting the at least one selected processor core further comprises:

selecting the at least one selected processor core from a selection pool of the plurality of processor cores;

if the accumulated usage for each processor core of the plurality of processor cores is greater than or equal to a first threshold of the core, then the selection pool consists of processor cores of the plurality of processor cores that are configurable to perform redundant operations with another processor core of the selection pool;

if the accumulated usage for each processor core of the plurality of processor cores is greater than or equal to the first threshold of the core, the performing the processor operation further comprises configuring a plurality of the selected processor cores for redundant operation for the performing the processor operation.

6 . The method of claim 5 further comprising:

after said performing, checking the results of the redundant operation in performing the processor operation to determine if the processor operation was performed correctly.

7 . The method of claim 5 wherein if the accumulated usage for any processor core is not greater than or equal to the first threshold of the processor core, the performing the processor operation does not include configuring a plurality of the selected processor cores for redundant operation for the performing the processor operation.

8 . The method of claim 5 if the accumulated usage of any processor core of the plurality is not greater than or equal to the first threshold of the processor core, the selection pool does not include any processor core with an accumulated usage greater than or equal to the first threshold of the processor core.

9 . The method of claim 1 wherein:

the selecting the at least one selected processor core further comprises selecting the at least one selected processor core from a selection pool of the plurality of processor cores;

the plurality of processor cores includes reserved processor cores and non reserved processor cores;

if the accumulated usage of any processor core of the plurality is not greater than or equal to the first threshold of the core, the selection pool does not include any reserved processor core with an accumulated usage greater than or equal to a second threshold of the reserved processor core and does include any non reserved processor core with an accumulated usage greater than or equal to the first threshold of the non reserved processor core;

wherein the first threshold is greater than the second threshold for the reserved processor cores.

10 . The method of claim 1 further comprising:

determining whether the processor operation requires reliability; and

if the processor operation does not require reliability, then the selecting at least one selected processor core further comprises selecting a processor core from a selection pool based on a highest accumulated usage to perform the processor operation.

11 . The method of claim 10 wherein:

if the processor operation does require reliability, then said selecting at least one selected processor core further comprises selecting a processor core based on a lowest accumulated usage to perform the processor operation.

12 . The method of claim 1 wherein if the accumulated usage for a processor core of the at least one processor core is greater than or equal to an error detection usage threshold of the processor core, the performing includes performing the processor operation with error detection enabled for the processor core.

13 . The method of claim 12 wherein if the accumulated usage for a processor core of the at least one processor core is less than the error detection usage threshold of the processor core, error detection is not enabled for the processor core in performing the processor operation.

14 . The method of claim 1 further comprising:

if the accumulated usage of a processor core of the at least one selected processor core is greater than or equal to an error detection enabling limit of the processor core, then:

the performing the processor operation includes performing the processor operation with error detection logging enabled for the processor core; and

storing the error detection logging information associated with the processor core in a storage device in response to a change in error detection logging information for the processor core.

15 . The method of claim 14 if the accumulated usage of the processor core is not greater than or equal to the error detection enabling limit of the processor core, then the performing the processor operation is performed without error detection logging being enabled for the processor core.

16 . The method of claim 14 further comprising:

pairing the processor core to another processor core of the plurality to perform a subsequent processor operation based on the error detection logging information.

17 . A data processor comprising:

a plurality of processor cores configured to perform data processing operations;

storage for accumulated usage information for each of the processor cores of the plurality of processor cores, wherein the accumulated usage information is indicative of accumulated usage of each processor core of the plurality of processor cores; and

a controller coupled to the plurality of processor cores and the storage and configured to select one or more selected processor cores from the plurality of processor cores to perform processor operations based on the accumulated usage information.

18 . The data processor of claim 17 further comprising:

a second storage for lifetime limit values for each of the plurality of processor cores, wherein the lifetime limit is characterized as a total amount of accumulated usage that a processor core can reliably perform, and

the controller is coupled to the second storage and further configured select one or more selected processor cores from the plurality of processor cores to perform processor operations using the accumulated usage information and the lifetime limit values.

19 . The data processor of claim 17 further comprising:

error detection circuitry configured to detect processing errors by the processor cores, and provide error information to the controller; and

the controller is further configured to selectively enable the error detection circuitry to detect a processing error by a processor core of the plurality of processor cores using the accumulated usage information for the processor core.

20 . The data processor of claim 17 further comprising:

a second storage for reservation limit values for each of a reservation set of processor cores of the plurality of processor cores, wherein a reservation limit value for an associated processor core of the reservation set is characterized as a threshold amount of accumulated usage for the associated processor core beyond which the associated processor core will not be selected to perform the processor operation unless other processor cores of the plurality of processor cores not of the reservation set exceed an associated lifetime limit; and

the controller is coupled to the second storage and further configured to select one or more selected processor cores from the plurality of processor cores to perform processor operations based on the accumulated usage information and the reservation limit values.

Assignments (27)
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040925 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Feb 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V. F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 052917/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 040928 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE RELEASE OF SECURITY INTEREST. Recorded Jan 17, 2020
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 052915/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 11759915 AND REPLACE IT WITH APPLICATION 11759935 PREVIOUSLY RECORDED ON REEL 037486 FRAME 0517. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Dec 10, 2019
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 053547/0421 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0387 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042985 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051029/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051030/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12298143 PREVIOUSLY RECORDED ON REEL 042762 FRAME 0145. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Oct 22, 2019
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 051145/0184 →
RELEASE OF SECURITY INTEREST Recorded Sep 10, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 050745/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE TO CORRECT THE APPLICATION NO. FROM 13,883,290 TO 13,833,290 PREVIOUSLY RECORDED ON REEL 041703 FRAME 0536. ASSIGNOR(S) HEREBY CONFIRMS THE THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS.. Recorded Feb 20, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: SHENZHEN XINGUODU TECHNOLOGY CO., LTD.
Reel/Frame 048734/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 039361 FRAME 0212. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042762/0145 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12681366 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded May 9, 2017
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 042985/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE PATENTS 8108266 AND 8062324 AND REPLACE THEM WITH 6108266 AND 8060324 PREVIOUSLY RECORDED ON REEL 037518 FRAME 0292. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS. Recorded Feb 1, 2017
From: CITIBANK, N.A.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 041703/0536 →
RELEASE OF SECURITY INTEREST Recorded Nov 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP B.V.
Reel/Frame 040928/0001 →
RELEASE OF SECURITY INTEREST Recorded Sep 21, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NXP, B.V., F/K/A FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 040925/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REMOVE APPLICATION 12092129 PREVIOUSLY RECORDED ON REEL 038017 FRAME 0058. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT SUPPLEMENT. Recorded Jul 14, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 039361/0212 →
SECURITY AGREEMENT SUPPLEMENT Recorded Mar 7, 2016
From: NXP B.V.
To: MORGAN STANLEY SENIOR FUNDING, INC.
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 13, 2016
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ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN PATENTS Recorded Jan 12, 2016
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
Reel/Frame 037357/0379 →
PATENT RELEASE Recorded Dec 21, 2015
From: CITIBANK, N.A., AS COLLATERAL AGENT
To: FREESCALE SEMICONDUCTOR, INC.
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SECURITY AGREEMENT Recorded Nov 6, 2013
From: FREESCALE SEMICONDUCTOR, INC.
To: CITIBANK, N.A., AS NOTES COLLATERAL AGENT
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SECURITY AGREEMENT Recorded Jun 18, 2013
From: FREESCALE SEMICONDUCTOR, INC.
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 7, 2012
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 7, 2012
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SUPPLEMENT TO IP SECURITY AGREEMENT Recorded Mar 7, 2012
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ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 13, 2011
From: MOYER, WILLIAM C.; BEARDEN, DAVID R.; RAMARAJU, RAVINDRARAJ
To: FREESCALE SEMICONDUCTOR, INC.
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