IP Library Granted Patent US 8,460,465
Granted Patent B2
US 8,460,465 · App. 13/274,456 · Granted Jun 11, 2013

Support ring for supporting a semiconductor wafer composed of monocrystalline silicon during a thermal treatment, method for the thermal treatment of such a semiconductor wafer, and thermally treated semiconductor wafer composed of monocrystalline silicon

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Quick Facts
Patent No.
US 8,460,465
App. No.
13/274,456
Granted
Jun 11, 2013
Kind
B2
Abstract

A support ring for supporting a monocrystalline silicon semiconductor wafer during a thermal treatment of the semiconductor wafer has outer and inner lateral surfaces and a curved surface extending from the outer lateral surface to the inner lateral surface, this curved surface serving for the placement of the semiconductor wafer. The curved surface has a radius of curvature of not less than 6000 mm and not more than 9000 mm for 300 mm diameter wafers, or a radius of curvature of not less than 9000 mm and not more than 14,000 mm for 450 mm diameter wafers. Use of the support ring during thermal treatment reduces slip and improves wafer nanotopography.

Claims (9)

1. A support ring for supporting a semiconductor wafer comprising monocrystalline silicon during a thermal treatment of the semiconductor wafer, the support ring having an external diameter and an internal diameter, comprising

a ring having an outer and an inner lateral surface and a curved surface extending from the outer to the inner lateral surface, the curved surface serving for placement of a semiconductor wafer, wherein the curved surface has a radius of curvature of not less than 6000 mm and not more than 9000 mm, if the curved surface is designed for placement of a semiconductor wafer having a diameter of 300 mm, or has a radius of curvature of not less than 9000 mm and not more than 14,000 mm, if the curved surface is designed for the placement of a semiconductor wafer having a diameter of 450 mm, and wherein the curved surface has a material proportion Rmr(t) of not less than 85% at a material depth t of 2 μm.

2. The support ring of claim 1 , wherein the curved surface has an average roughness depth Rz of not less than 3 μm and not more than 5 μm and a maximum individual roughness depth Rmax of not more than 5 μm.

3. The support ring of claim 1 , wherein the surface form tolerance of the curved surface is not more than 0.03 mm.

4. The support ring of claim 1 , wherein the external diameter of the support ring is equal to the diameter of a semiconductor wafer to be treated or is greater by not more than 2 mm, and the internal diameter of the support ring is not less than 60 mm and not more than 100 mm smaller than the external diameter.

5. The support ring of claim 1 , wherein the support ring is constructed from silicon carbide or is coated with silicon carbide.

6. A method for the thermal treatment of a semiconductor wafer of monocrystalline silicon, comprising placing the semiconductor wafer on a support ring having an external diameter and an internal diameter, comprising

a ring having an outer and an inner lateral surface and a curved surface extending from the outer to the inner lateral surface, the curved surface serving for placement of a semiconductor wafer, wherein the curved surface has a radius of curvature of not less than 6000 mm and not more than 9000 mm, if the curved surface is designed for placement of a semiconductor wafer having a diameter of 300 mm, or has a radius of curvature of not less than 9000 mm and not more than 14,000 mm, if the curved surface is designed for the placement of a semiconductor wafer having a diameter of 450 mm, and wherein the curved surface has a material proportion Rmr(t) of not less than 85% at a material depth t of 2 μm and heating the semiconductor wafer positioned on the support ring to a temperature of not less than 1050° C. and not more than 1300° C. for a time period of not less than 30 min and not more than 180 min.

7. An uncoated semiconductor wafer having a front side and a back side, composed of monocrystalline silicon having a denuded zone on at least one surface thereof, formed by a heat treatment, the silicon wafer having a nitrogen concentration of not less than 1×10 13 atoms/cm 3 and not more than 8×10 14 atoms/cm 3 and having a nanotopography of the front side of the semiconductor wafer of less than 20 nm relative to a circular measurement window having a diameter of 4 mm, and less than 40 nm relative to a circular measurement window having a diameter of 20 mm.

Assignments (3)
CORRECTIVE ASSIGNMENT TO CORRECT THE DATE OF THE CHANGE OF ADDRESS FROM 03/12/2020 TO 12/03/2020 PREVIOUSLY RECORDED AT REEL: 056719 FRAME: 0881. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Jul 1, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 057561/0451 →
CHANGE OF ADDRESS Recorded Jun 30, 2021
From: SILTRONIC AG
To: SILTRONIC AG
Reel/Frame 056719/0881 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 17, 2011
From: DAUB, ERICH; KAISS, RAIMUND; KLOESLER, MICHAEL; LOCH, THOMAS
To: SILTRONIC AG
Reel/Frame 027069/0775 →